Fujitsu MB89140 Series Hardware Manual page 81

12-BIT MULTIPUL
GENERATOR
(MPG, TIMER 4)
Address: 0024 MCNT
H
Address: 0025 INTSTR
H
Address: 0026
H
CMCLBR CMCLBR
(H)
Address: 0027
H
CMCLR CMCLR
(H)
Address: 0028
H
OUTCBR OUTCBR
(H)
Address: 0029
H
OUTCR OUTCR
(H)
Address: 0024 MCNT
H
Address: 0025 INTSTR
H
Address: 0026
H CMCLBR CMCLBR
(H)
Address: 0027
H
CMCLR CMCLR
(H)
Address: 0028
H
OUTCBR OUTCBR
(H)
Address: 0029
H
OUTCR OUTCR
(H)
HARDWARE CONFIGURATION
(3) Compare clear register (CMCLR)
This register is used to store the compare value of compare clear.
When the values of this register and timer agree, the timer is cleared. The
value is transferred from the buffer register to the compare register.
Bit 15
—
(L)
(L)
Bit 7
CLR7
(L)
(L)
In the PPG operation mode, the match between the value of this register + 1
and the value of the timer is detected to clear the timer and set the MPG out-
put.
In the PWM operation mode, the match between the value of this register + 1
and the value of the timer is detected to clear the timer and set the MPG out-
put.
(4) Compare clear buffer register (CMCLBR)
This register is used to store the compare value of compare clear.
The value written to the compare clear buffer register when the timer stops
is written directly to the compare clear register.
(L)
Data transfer from the compare clear buffer register to the compare clear
register after the timer starts is done when the compare clear match oc-
(L)
curs.
Bit 15
(L)
Address: 0026
—
H
(L)
Bit 7
Address: 0027
CLR7
H
(W)
Note: To write the value to the output compare register buffer register during
PWM or PPG operation, use the load instruction. Some time should
be taken to allow writing of the load instruction to terminate until the
values of the compare clear register and timer agree.
2-61
Bit 14 Bit 13 Bit 12 Bit 11
— — — CLRB
Bit 6 Bit 5 Bit 4 Bit 3
CLR6 CLR5 CLR4 CLR3
Bit 14 Bit 13 Bit 12 Bit 11
— — — CLRB
(W)
Bit 6 Bit 5 Bit 4 Bit 3
CLR6 CLR5 CLR4 CLR3
(W) (W) (W) (W)
Bit 10 Bit 9 Bit 8
CLRA CLR9 CLR8
Initial value
----0000
B
Bit 2 Bit 1 Bit 0
CLR2 CLR1 CLR0
Initial value
00000000
B
Bit 10 Bit 9 Bit 8
CLRA CLR9 CLR8
(W) (W) (W)
Initial value
----0000
B
Bit 2 Bit 1 Bit 0
CLR2 CLR1 CLR0
(W) (W) (W)
Initial value
00000000
B