Fujitsu MB89140 Series Hardware Manual page 57

WATCHDOG TIMER
RESET
HARDWARE CONFIGURATION
[Bit 7] CS: Clock source switching bit
This bit is used to select a count clock from either the watch prescaler or
time-base timer.
Time-base timer cycle = 1/2
0
Watch prescaler cycle = 1/2
1
Note: Set this bit as soon as the watchdog timer is started. Do not change
the bit after the timer is started. When using the submode, always
select the watch prescaler. Do not select the watchdog prescaler for
the single-circuit clock.
[Bit 6] WDOS: Watchdog output select bit
Bit 6 is used to select output from the pin when the watchdog timer causes a
time-out. (This function cannot be used when the power-on reset unavail-
able option is selected, write 0 in this case.)
0
Output from RST pin (P23 as general-purpose output pin; reset occurs)
1
Output from P23/WDG pin (reset does not occur)
Note: This bit is not cleared by the reset conditions. This register is cleared
only by a power-on reset.
[Bit 5] WDGF: Watchdog output set bit
Bit 5 is set to 1 when a time-out of the watchdog timer is detected. In this
case, the WDG signal is output when the WDOE is 1. Clearing this bit stops
output of the WDG signal. (This function cannot be used when the power-on
reset unavailable option is selected, write 0 in this case).
The meaning of each bit to be read is as follows:
0
No operation
1
Time-out detected by watchdog timer (WDG output)
1 is always read when the Read Modify instruction is read.
The meaning of each bit to be written is as follows:
0
This bit is cleared.
1
This bit does not change or affect other bits.
Note: This bit is not cleared by the reset conditions. This register is cleared
only by a power-on reset.
2-37
22
/f
CH
14
/f
CL
f : Main clock frequency
CH
f : Subclock frequency
CL