Fujitsu MB89140 Series Hardware Manual page 43

INTERRUPT
CONTROLLER
Address: 007C ILR1
H
Address: 007D ILR2
H
Address: 007E ILR3
H
[Example]
Interrupt requests
from resources
HARDWARE CONFIGURATION
Description of Registers
The detail of each register is described below.
Interrupt level register (ILRX: Interrupt Level Register X)
Bit 7
L31
Address: 007C
H
Address: 007D L71
H
LB1
Address: 007E
H
(W)
The ILRX sets the interrupt level of each resource. The digits in the center of
each bit correspond to the interrupt numbers.
L3X
Interrupt control module
IR0
IR1
IR2
IR3
IRB
When an interrupt is requested from a resource, the interrupt controller
transfers the interrupt level based on the value set at the 2-bits of the ILRX
corresponding to the interrupt to the CPU. The relationship between the 2
bits of the ILRX and the required interrupt levels is as follows:
Lx1 Lx0
0
1 0
1 1
2-23
Bit 6 Bit 5 Bit 4 Bit 3
L30 L21 L20 L11
L70 L61 L60 L51
LB0 LA1 LA0 L91
(W) (W) (W) (W)
MB89140 hardware manual
Required interrupt level
1
2
3 (None)
Bit 2 Bit 1 Bit 0
L10 L01 L00
L50 L41 L40
L90 L81 L80
(W) (W) (W)
Initial value
11111111
B
Interrupt Table address
number
Upper Lower
#0 FFFA FFFB
#1 FFF8 FFF9
#2 FFF6 FFF7
#3 FFF4 FFF5
#11 FFE4 FFE5