Fujitsu MB89140 Series Hardware Manual page 64

8-Bit PWM TIMER
(TIMER 1)
Address: 0016 COMR
H
Address: 0017 CNTR
H
(One system clock is 500 ns at 8.0 MHz and maximum gear speed.)
HARDWARE CONFIGURATION
Description of Register
The detail of watch prescaler is described below.
(1) Control register (CNTR)
Bit 7
P/TX
Address: 0017
H
(R/W)
[Bit 7] P/TX: Timer/PWM operation switching bit
The operation is performed as the timer when this bit is set to 0, and as the
PWM controller when bit 7 is set to 1.
0 Timer
1 PWM controller
The timer/PWM operation mode should be switched when the counter op-
eration is stopped (TPE = 0), the interrupt is enabled (TIE =0), and the inter-
rupt request flag is cleared (TIR = 0).
[Bits 5 and 4] P1, P0: Clock select bit
The following four system clock cycles can be selected by P1 and P0.
System clock cycle
P1 P0
of PWM timer
0 0 1 system clock cycle
0 1 2 system clock cycles
1 0 8 system clock cycles
1 1 16 system clock cycles
These bits must not be rewritten during counting (TPE = 1).
[Bit 3] TPE: Counter operation enable bit
When Bit 3 is set to 1, the timer or PWM control circuit starts operation.
0 Counting stop
1 Counting start
[Bit 2] TIR: Interrupt request flag bit
When an interrupt source occurs, Bit 2 goes to 1. To clear the generated
interrupt source, write 0 at this bit.
The meaning of each bit to be read is as follows:
0 Counter and CMR values do not agree
1 Counter and CMR values agree
2-44
Bit 6 Bit 5 Bit 4 Bit 3
— P1 P0 TPE
(R/W) (R/W) (R/W)
Maximum gear speed
Bit 2 Bit 1 Bit 0
TIR OE TIE
(R/W) (R/W) (R/W)
Initial value
0-000000
B
At 8 MHz and
0.5 µs
1.0 µs
4.0 µs
8.0 µs