Fujitsu MB89140 Series Hardware Manual page 106

EXTERNAL INTERRUPT
CIRCUIT
HARDWARE CONFIGURATION
[Bit 7] EIR1: External-interrupt request flag
When the edge specified by the SL10 and SL11 bits is input to the INT1 pin,
bit 7 is set to 1. When the EIE1 bit is 1, an interrupt request (IRQ1) is output if
this bit is set.
The meaning of each bit to be read is as follows:
0 Specified edge not input to INT1 pin
1 Specified edge input to INT1 pin (IRQ1 is output.)
1 is always read when the Read Modify Write instruction is read.
The meaning of each bit to be written is as follows:
0 This bit is cleared.
1 This bit does not change nor affect other bits.
[Bit 6 and Bit 5] SL11, SL10: Edge-polarity mode select bit
These bits are used to control the input edge polarity of the INT1 pin.
SL11 SL10 Selection of external interrupt enable edge
Both-edge mode
1
Rising edge
0 1
Falling edge
0 0
[Bit 4] EIE1: Interrupt-enable bit
This bit is used to enable an external-interrupt request by the INT1 pin.
0 Interrupt request disabled
1 Interrupt request enabled by EIR1 setting
[Bit 3] EIR0: External-interrupt request flag
When the edge specified by the SL00 and SL01 bits is input to the INT0 pin,
bit 3 is set to 1. When the EIE0 is 1, an interrupt request (IRQ0) is output if
this bit is set.
The meaning of each bit to be read is as follows:
Specified edge not input to INT0 pin
0
Specified edge input to INT0 pin (IRQ0 is output.)
1
1 is always read when the Read Modify Write instruction is read.
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