Interrupt; Fig. 3.4 Interrupt-Processing Flowchart - Fujitsu MB89140 Series Hardware Manual

3.3 INTERRUPT

If the interrupt controller and CPU are ready to accept interrupts when an interrupt request is output from the
internal resources or by an external-interrupt input, the CPU temporarily suspends the currently-executing
instruction and executes the interrupt-processing program. Figure 3.4 shows the interrupt-processing flow-
chart.
Internal bus
Register file
IPLA
(8)
(5)
Enable FF
Source FF
(6) (1)
Resource
All interrupts are disabled after a reset is cleared. Therefore, initialize interrupts in the main program (1). Each
resource generating interrupts and the interrupt-level-setting registers (ILR1 to ILR3) in the interrupt controller
corresponding to these interrupts are to be initialized. The levels of all interrupts can be set by the interrupt-
level-setting registers (ILR1 to ILR3) in the interrupt controller. The interrupt level can be set from 1 to 3, where
1 indicates the highest level, and 2 the second highest level. Level 3 indicates that no interrupt occurs. The
interrupt request of this level cannot be accepted. After initializing the registers, the main program executes
various controls (2). Interrupts are generated from the resources (3). The highest-priority interrupt requests
are identified from those occurring at the same time by the interrupt controller and are transferred to the CPU.
The CPU then checks the current interrupt level and the status of the I-flag (4), and starts the interrupt proces-
sing.
The CPU performs the interrupt processing to save the contents of the current PC and PS in the stack (5) and
fetches the entry addresses of the interrupt program from the interrupt vectors. After updating the IL value in
the PS to the required one, the CPU starts executing the interrupt-processing routine.
Clear the interrupt sources (6) and process the interrupts in the user's interrupt-processing routine. Finally,
restore the PC and PS values saved by the RETI instruction in the stack (8) to return to the interrupted instruc-
tion.
2
Note: Unlike the F MC-8 family, A and T are not saved in the stack at the interrupt time. If interrupts of the
same level occur at the same time, IRQ0 takes precedence.
OPERATION
PS I IL
IR Check Comparator
(4)
MB8914X CPU
RAM
Level
comparator
AND
(3)
Interrupt controller

Fig. 3.4 Interrupt-processing Flowchart

3-6
Main program
PC, PS saved
Reset clear
(4)
(4)
Level
(1) Initialize
decided
interrupt
(2) Execute
(4)
main program
PC, PS restored
Interrupt
processing
(5)
IL updated
(6) Clear request
(3)
(7) Interrupt
Interrupt
processing
generation
Restore PC, PS
RETI
(8)