Fujitsu MB89140 Series Hardware Manual page 37

MAIN/SUBCLOCK
CONTROL BLOCK
HARDWARE CONFIGURATION
Canceling SLEEP mode
– The SLEEP mode is canceled by inputting the reset signal and re-
questing an interrupt.
– When the reset signal is input during the SLEEP mode, the CPU is
switched to the reset state and the SLEEP mode is canceled.
– When an interrupt level higher than 11 is requested from a resource
during the SLEEP mode, the SLEEP mode is canceled.
– When the I flag and IL bit are enabled like an ordinary interrupt after
canceling, the CPU executes the interrupt processing. When they are
disabled, the CPU executes the interrupt processing from the instruc-
tion next to the one before entering the SLEEP mode.
(c) STOP mode
Switching to STOP mode
– Writing 1 at the STP bit (bit 7) of the STBC register switches the mode
to STOP mode.
– The STOP mode varies when the main clock is operating and when the
subclock is operating.
When the main clock is operating: The main clock stops but the sub-
clock does not stop. All chip functions except the watch function stop.
However, no watch interrupt can be accepted.
When subclock is operating: Both the main clock and subclock stop. All
chip functions stop.
– The input/output pins and output pins during the STOP mode can be
controlled by the SPL bit (bit 5) of the STBC register so that they are
held in the mode immediately before entering the STOP mode, or so
that they enter in the high-impedance state.
– If an interrupt is requested when 1 is written at the STP bit (bit 7),
instruction execution continues without switching to the STOP mode.
– In the STOP mode, the values of registers and RAM immediately be-
fore entering the STOP mode are held.
Canceling STOP mode
– The STOP mode is canceled either by inputting the reset signal or by
requesting an interrupt.
– When the reset signal is input during the STOP mode, the CPU is
switched to the reset state and the STOP mode is canceled.
– When an interrupt higher than level 11 is requested from the external
interrupt circuit during the STOP mode, the STOP mode is canceled.
– When the I flag and IL bit are enabled like an ordinary interrupt after
canceling, the CPU executes the interrupt processing. When they are
disabled, the CPU executes the interrupt processing from the instruc-
tion next to the one before entering the STOP mode.
– Four oscillation stabilization times of the main clock can be selected by
the WT1 and WT0 bits. The oscillation stabilization time of the sub-
15
clock is fixed (at 2 /f
2-17
— f : frequency of subclock).
CH CH