Fig. 2.32 Outline Of Pwm Output; Fig. 2.33 Description Of Pwm Output Operation - Fujitsu MB89140 Series Hardware Manual

12-BIT MULTIPUL
GENERATOR
(MPG, TIMER 4)
HARDWARE CONFIGURATION
Operation description
(1) PWM operation (counting)
Timer value
Set value to CMCLR + 1
Set value to OUTCR
00
H
MPG output

Fig. 2.32 Outline of PWM Output

As shown in Figure 2.32, the MPG can generate a PWM waveform. The
repeat cycle is set by the value of the compare clear register, and the duty of
the output pulse is set by the value of the output compare register.
(Software or external)
trigger input
Timer value
03FF
H
02FF
H
01FF
H
00FF
H
Compare clear buffer
(01FE)
register (CMCLBR)
Compare clear
(01FE)
register (CMCLR)
Output compare buffer
(00FF)
register (OUTCBR)
Output compare
(00FF)
register (OUTCR)
MPG output
PW00 pin output
(SPOL = 1)

Fig. 2.33 Description of PWM Output Operation

2-63
Output compare match
Compare clear timer match
H
H
H
H
OUTCR CMCLR OUTCR
Match Match Match
Transfer
(03FE)
H
(03FE)
H
(02FF)
H
(02FF)
H
CMCLR OUTCR
Match Match
Transfer