Fujitsu MB89140 Series Hardware Manual page 98

A/D CONVERTER
Address: 001E ADC1
H
Address: 001F ADC2
H
Address: 0020 ADDH
H
Address: 0021 ADDL
H
Conversion time at 8 MHz and
TIM1 TIM0
33 system clock cycles (16.5 µs)
0 0
48 system clock cycles (24.0 µs)
0 1
66 system clock cycles (33.0 µs)
1 0
90 system clock cycles (45.0 µs)
1 1
HARDWARE CONFIGURATION
When reading this bit with the Read Modify Write instructions, 1 is always
read.
[Bit 2] ADMV: Processing progress flag
Bit 2 indicates the progress of conversion or comparison processing.
Converting and processing not progressing
0
Converting and processing progressing
1
[Bit 1] SIFM: Interrupt source setting bit
This bit is used to set the conditions for setting interrupt source conversion in
the sense mode.
Set interrupt source when input voltage lower than voltage
0
set by ADCD register.
Set interrupt source when input voltage higher than volt-
1
age set by ADCD register.
[Bit 0] AD: A/D conversion start bit
In both the A/D and sense modes, writing 1 at this bit starts A/D conversion
when the EXT bit (bit 1) of the ADC2 is 0. Writing 0 at this bit has no meaning.
0 is always read. The meaning of each bit to be written is as follows:
No change
0
A/D conversion start (When EXT bit (bit 1) of ADC2 is 0)
1
(2) A/D converter control register 2 (ADC2)
The ADC2 is used to control the A/D converter and to indicate its operation
status.
Bit 7
—
Address: 001F
H
[Bits 6 and 5] TIM1, TIM0: Conversion/comparison time select bits
Bits 6 and 5 are used to select the conversion time or comparison time.
maximum gear speed
2-78
Bit 6 Bit 5 Bit 4 Bit 3
TIM1 TIM0 ADCK ADIE
(R/W) (R/W) (R/W) (R/W)
Comparison time at 8 MHz and
maximum gear speed
18 system clock cycles (9.0 µs)
33 system clock cycles (16.5 µs)
51 system clock cycles (25.5 µs)
75 system clock cycles (37.5 µs)
Bit 2 Bit 1 Bit 0
ADMD EXT TEST
(R/W) (R/W) (R/W)
Initial value
00000001
B