Fujitsu MB89140 Series Hardware Manual page 38

MAIN/SUBCLOCK
CONTROL BLOCK
HARDWARE CONFIGURATION
– If the STOP mode is canceled by inputting the reset signal, the CPU is
switched to the oscillation stabilization wait state. Therefore, the reset
sequence is not executed unless the oscillation stabilization time is
elapsed. The oscillation stabilization time corresponds to the oscillation
stabilization time of the main clock selected by the WT1 and WT0 bits.
However, when Power-on Reset is not specified by the mask option, the
CPU is not switched to the oscillation stabilization wait state even if the
STOP mode is canceled by inputting the reset signal.
(2) Setting low power consumption mode
STBC Register
STP (Bit 7) SLP (Bit 6)
0 0
0 0
0 1
1 0
1
Note: When the mode is switched from the subclock mode to the main clock
mode, do not set the Stop, Sleep, and Watch modes. If the SCS bit of
the SYCC register is rewritten from 0 to 1, set the above modes after
the SCM bit of the SYCC register has been set to 1.
2-18
Mode
TMD (Bit 3)
0 Normal
1 WATCH
0 SLEEP
0 STOP
Disable