Fig. 2.9 Interrupt Controller Block Diagram - Fujitsu MB89140 Series Hardware Manual

INTERRUPT
CONTROLLER
2
F MC-8L bus
Test
register
Resource #1 G
Resource #2 G
Resource #n G
HARDWARE CONFIGURATION
2.3 INTERRUPT CONTROLLER
The interrupt controller for the F
2
F MC-8L CPU and each resource. This controller receives interrupt re-
quests from the resources, assigns priority to them, and transfers the
priority to the CPU; it also decides the priority of same-level interrupts.
Block Diagram
Address decorder
L Level
L Level
L Level

Fig. 2.9 Interrupt Controller Block Diagram

Register List
Interrupt controller consists of interrupt-level registers (ILR1, 2, and 3).
Address: 007C
H
Address: 007D
H
Address: 007E
H
2-22
2
MC-8L family is located between the
CPU
2
G
Level Same level
G
deciding priority order
block deciding
block
G
8 bit
W Interrupt level register #1
ILR1
W Interrupt level register #2
ILR2
ILR3 W Interrupt level register #3
Interrupt
vector
generation
block