Fujitsu MB89140 Series Hardware Manual page 99

A/D CONVERTER
Address: 001E ADC1
H
Address: 001F ADC2
H
Address: 0020 ADDH
H
Address: 0021 ADDL
H
HARDWARE CONFIGURATION
[Bit 4] ADCK: External input clock pulse select bit
Bit 4 is used to select the clock pulse for starting by the external input clock
pulse.
No change
0
Operation started (when EXT bit (bit 1) of ADC2 is 1)
1
[Bit 3] ADIE: Interrupt specification bit
This bit is used to specify interrupt enable/disable.
Interrupt disabled
0
Interrupt enabled
1
[Bit 2] ADMD: Function-switching bit
This bit is used to switch the A/D mode and sense mode.
A/D mode
0
Sense mode
1
[Bit 1] EXT: Start type select bit
Bit 1 is used to select the conversion start type.
Starts A/D conversion with AD bit (bit 0) of ADC1
0
Starts A/D conversion at rising edge of clock selected by
1
ADCK bit (bit 4) of ADC2
[Bit 0] TEST: Test bit
This bit is used only for testing. Always write 1 at this bit. 1 is always read.
(3) A/D data registers H and L (ADDH and ADDL)
These registers are used to store the results of A/D conversion in A/D mode
and write the comparison set value in the Sense mode. Two upper bits and
eight lower bits are assigned to the ADDH and ADDL, respectively.
Bit 7 Bit 6
— —
Address: 0020
H
Address: 0021 7 6
H
(R/W) (R/W)
2-79
Bit 5 Bit 4 Bit 3 Bit 2
— — — —
5 4 3 2
(R/W) (R/W) (R/W) (R/W)
Bit 1 Bit 0
9 8
(R/W) (R/W)
Initial value
000000XX
B
1 0
(R/W) (R/W)
Initial value
XXXXXXXX
B