Fig. 2.12 Ports 14 To 16; Fig. 2.13 Ports 20 To 23 - Fujitsu MB89140 Series Hardware Manual

I/O PORTS
Internal data bus
PDR
PDR read
PDR read
(when Read Modify Write instruction executed)
PDR write
DDR write
Internal data bus
PDR
PDR read
PDR write
HARDWARE CONFIGURATION
State in stop modes
With the SPL bit of the standby-control register set to 1, in the stop mode,
the output impedance goes High irrespective of the value of the DDR.
Output latch
DDR
Stop mode (SPL = 1)

Fig. 2.12 Ports 14 to 16

(3) P20 to P23: CMOS-type output ports
(used as resource output, excluding P20 and P22)
Operation for output port
The value written at the PDR is output to the pin. Since the content of the
output latch is always read when the PDR is read, the bit-processing
instruction can be used even if the output level varies with load.
Resource output operation (P23 and P21)
When using as the resource output, setting is performed by the resource
output enable bit. (See the description of each resource.)
State when reset
At reset, all pins are set to High impedance. When a vector is fetched, the
output from each port is enabled and all pins start serving as output ports.
At reset, the PRD is initialized to 0 and Low level is output at all pins.
State in stop modes
With the SPL bit of the standby-control register set to 1, in the stop mode,
the output impedance goes High irrespective of the value of the DDR.
Output latch
P20 and P22 excluded
Stop mode (SPL = 1)

Fig. 2.13 Ports 20 to 23

2-29
Input buffer (hysteresis)
Output buffer
Resource output
Resource
output enabled
Pull-up resistor
(option)
Pin
Pin