Fujitsu MB89140 Series Hardware Manual page 62

TIME-BASE TIMER
Address: 000A TBCR
H
TBC1 TBC0
0
0
1
1
HARDWARE CONFIGURATION
Description of Registers
The detail of time-base timer control register (TBCR) is described below.
(1) Time-base timer control register (TBCR)
Bit 7
TBOF
Address: 000A
H
(R/W)
[Bit 7] TBOF: Interval timer overflow bit
When writing, this bit is used to clear the interval timer overflow flag.
Interval timer overflow flag cleared
0
No operation
1
When reading, this bit indicates that an interval timer overflow has occurred.
Interval timer overflow not occurred
0
Interval timer overflow occurred
1
1 is read when the Read Modify Write instruction is read. If the TBIF bit is set
to 1 when the TBIE bit is 1, an interrupt request is output. This bit is cleared
upon reset.
[Bit 6] TBIE: Interval-timer interrupt enable bit
This bit is used to enable an interrupt by the interval timer.
Interval interrupt disabled
0
Interval interrupt enabled
1
[Bit 2 and 1] TBC1, TBC2: Interval time specification bit
These bits are used to specify interval timer cycle.
Interval time
0.26 ms
0
0.51 ms
1
1.02 ms
0
0.524 s
1
[Bit 0] TBR: Time-base timer clear bit
This bit is used to clear time-base timer.
Time-base timer cleared
0
No operation
1
1 is always read when this bit is read.
2-42
Bit 6 Bit 5 Bit 4 Bit 3
TBIE — — —
(R/W)
8 MHz source clock
f
Bit 2 Bit 1 Bit 0
TBC1 TBC0 TBR
(R/W) (R/W) (W)
Initial value
00---000
B
11
2 /f
CH
12
2 /f
CH
13
2 /f
CH
22
2 /f
CH
: main clock frequency
CH