Fujitsu MB89140 Series Hardware Manual page 89

HARDWARE CONFIGURATION
Value set at OUTCBR count clock cycle + 1.5 to 2 system clock cycles
12-BIT MULTIPUL
GENERATOR
The time from external trigger input to MPG reset is as follows:
(MPG, TIMER 4)
(Value set at CMCLR +1) count clock cycle + 1.5 to 2 system clock cycles
For CMCLR OUTCR, the MPG output is in the set state and the pulse is not
output. For (OUTCR 0, CMCLR = 0), the MPG output is also in the set
state.
When the value of the OUTCR agrees with the value of the CMCLR +1, the
comparison with the value of the CMCLR + 1 proceeds and the MPG output
is set.
The polarity of the output pulse can be changed by setting the SPOL bit. The
set value must not be changed during pulse output. The operation flow for
PPG output is shown in Figure 2.37.
The DTTI input pin is provided to inactivate the PPG output inactive at hard-
ware in the event of an external error. When the DTTI input is set to effective,
when an error is detected, the DTIR flag is set to inactivate the PPG output.
The time required for this operation is 6 to 8 clock cycles (one system clock
cycle is 500 ns at 8 MHz and maximum gear speed).
To restart the PPG output after recovery from an error, the DTIR flag must be
cleared to input the effective trigger. In the event of an interrupt at DTTI in-
put, other interrupt sources may be set. Therefore, to restart, all MPG inter-
rupt sources should be cleared.
Since the DTTI input is edge input, the rising or falling edge can be selected.
The DTTI input block has a noise filter.
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