Fujitsu MB89140 Series Hardware Manual page 92

8-BIT SERIAL I/O
CKS1 CKS0
0 0
0 1
1 0
1 1
Note: One system clock cycle is 500 ns at 8 MHz and maximum gear speed.
Address: 001C SMR
H
Address: 001D SDR
H
HARDWARE CONFIGURATION
[Bit 4] SOE: Serial-data output-enable bit
This bit is used to control the output pin for serial I/O.
0 General-purpose port pin (P33)
1 SO (serial data) output pin
When using P34/SI pin as SI pin, always set the DDR to input (bit 0 of DDR4
= 0).
[Bits 3 and 2] CKS1, CKS0: Shift-clock select bits
These bits are used to select the serial shift-clock modes.
Mode
Internal shift-clock mode
Internal shift-clock mode
Internal shift-clock mode
External shift-clock mode
[Bit 1] BDS: Transfer direction select bit
At serial data transfer, this bit is used to select whether data transfer is per-
formed from the least significant bit first (LSB first) or from the most signifi-
cant bit first (MSB first).
LSB first
0
MSB first
1
Note that when this bit is rewritten after writing data to the SDR, the data be-
come invalid.
[Bit 0] SST: Serial I/O transfer-start bit
This bit is used to start serial I/O transfer. The bit is automatically cleared to
0 when transfer is terminated.
Serial I/O transfer stop
0
Serial I/O transfer start
1
Before starting transfer, ensure that transfer is stopped (SST = 0).
(2) Serial-data register (SDR)
This 8-bit register is used to hold serial I/O transfer data. Do not write data
to this register during the serial I/O operation.
Bit 7 Bit 6
Address: 001D
H
(R/W) (R/W)
2-72
Clock cycle at maximum
gear speed
4 system clock cycle
8 system clock cycle
16 system clock cycle
SCK
Bit 5 Bit 4 Bit 3 Bit 2
(R/W) (R/W) (R/W) (R/W)
SCK
Output
Output
Output
Input
Bit 1 Bit 0
(R/W) (R/W)
Initial value
XXXXXXXX
B