Fujitsu MB89140 Series Hardware Manual page 80

12-BIT MULTIPUL
GENERATOR
(MPG, TIMER 4)
HARDWARE CONFIGURATION
[Bit 5] CLIE: Compare clear match interrupt enable bit
Bit 5 is used to enable the compare clear match interrupt request.
0 Compare clear match interrupt request disabled
1 Compare clear match interrupt request enabled
[Bit 4] CLIR: Compare clear match interrupt request flag
Bit 4 is set to 1 when the compare clear match occurs.
Writing 0 clears this bit.
Writing 1 has no meaning.
1 is always read when the Read Modify Write instruction is read.
0 Compare clear match interrupt not requested
1 Compare clear match interrupt requested
[Bit 3] CMIE: Output compare match interrupt enable bit
Bit 3 is used to enable the compare match interrupt.
0 Output compare match interrupt request disabled
1 Output compare match interrupt request enabled
[Bit 2] CMIR: Output compare match interrupt request flag
Bit 2 is set to 1 when the compare match occurs.
Writing 0 clears this bit.
Writing 1 has no meaning.
1 is always read when the Read Modify Write instruction is read.
0 Output compare match interrupt not requested
1 Output compare match interrupt requested
[Bit 1] DTIE: Overcurrent detection interrupt enable bit
Bit 1 is used to enable the overcurrent detection interrupt request.
0 Overcurrent detection interrupt request disabled
1 Overcurrent detection interrupt request enabled
[Bit 0] DTIR: Overcurrent detection interrupt request flag
Bit 0 is set to 1 when the effective rising/falling edge is input to the DTTI input
pin. This bit is not set when the PCN1 bit of the MCNT register is 0.
Writing 0 clears this bit.
Writing 1 has no meaning.
1 is always read when the Read Modify Write instruction is read.
0 No effective input to DTTI input pin
1 Effective input to DTTI input pin
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