Appendix A I/O Map - Fujitsu MB89140 Series Hardware Manual

APPENDIX A I/O MAP

Addresses 00 to17
H H
Address Read/Write
00 (R/W)
H
01 (W)
H
02 (R/W)
H
03 (W)
H
04 (R/W)
H
05 Reserved
H
06 Reserved
H
07 (R/W)
H
08 (R/W)
H
09 (R/W)
H
0A (R/W)
H
0B (R/W)
H
0C (R/W)
H
0D (W)
H
0E (R/W)
H
0F (R/W)
H
10 (R/W)
H
11 (R/W)
H
12 (R/W)
H
13 (W)
H
14
H
15
H
16 (W)
H
17 (R/W)
H
See each section describing the block of the registers for each register function.
APPENDIX
Initial value
Register
MSB LSB
PDR0 XXXX XXXX Port 0 data register
DDR0 0000 0000
PDR1 XXXX XXXX Port 1 data register
DDR1 0000 0000
PDR2 - - - - 0000
— —
— —
SYCC X - - 1 1111
STBC 00001 0 - - - Standby control register
WDTC 000 - XXXX Watchdog timer control register
TBCR 00 - - - 000
WPCR 00 - - - 000
PDR3 XXXX XXXX Port 3 data register
DDR3 0000 0000
BUZR - - - - - - 00
EIC 0000 0000
PDR4 0000 0000
PDR5 0000 0000
PDR6 0000 0000
PDR7 - - - - - - 00
COMR XXXX XXXX 8-bit PWM timer compare register
CNTR 0 - 00 0000
App.- 3
Description of register
Port 0 data direction register
Port 1 data direction register
Port 2 data register
Access disable
Access disable
System clock control register
Time-base timer control register
Watch prescaler control register
Port 3 data direction register
Buzzer register
External interrupt control register
Port 4 data register
Port 5 data register
Port 6 data register
Port 7 data register
8-bit PWM timer control register