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8-BIT SERIAL I/O
SDR
#7
Shift-clock pulse
CK
SDR
#7
Shift-clock pulse
CK
SI
SI
HARDWARE CONFIGURATION
Description of Operation
The operation of 8-bit serial I/O is described below.
(1) Outline
This module consists of the serial-mode register (SMR) and serial-data reg-
ister (SDR). At serial output, data in the SDR is output in bit serial to the seri-
al output pin (SO) in synchronization with the falling edge of a serial shift-
clock pulse generated from the internal or external clock. At serial input,
data is input in bit serial from the serial input pin (SI) to the SDR at the rising
edge of a serial shift-clock pulse.
#6
#5
#4
#3
#2
#1
#0
P
S conversion
#6
#5
#4
#3
#2
#1
#0
S
P conversion
(2) Operation modes
The serial I/O has three internal shift-clock modes and one external shift-
clock mode according to the type of shift-clock, which are specified by the
SMR. Mode switching or clock selection should be made with serial I/O
stopped (SST bit (bit 0) of SMR = 0).
Internal shift-clock mode
Operation is performed by the internal clock. A shift-clock pulse with a duty
of 50% is output from the SCK pin as a synchronous timing output. Data is
transferred bit-by-bit at every clock pulse.
External shift-clock mode
Data is transferred bit-by-bit at every clock pulse in synchronization with
the external shift-clock pulse input from the SCK pin. The transfer rate can
be performed from DC to 8 clock cycles (1.00 MHz at 8 MHz).
Do not write data to the SMR and SDR during the serial I/O operation in ei-
ther mode.
2-73
Shift-clock pulse
SO
#0
0
SO
Shift-clock pulse
SI
#0
#1
#2
#5
#6
#7
Serial output
#1
#2
#5
#6
#7
Serial input
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