Clock Generation - Xilinx KC705 User Manual

Chapter 1: KC705 Evaluation Board Features

Clock Generation

There are five clock sources available for the FPGA fabric on the KC705 board (refer to
Table
Table 1-8: KC705 Board Clock Sources
System Clock
User Clock
User SMA Clock
(differential pair)
GTX SMA REF Clock
(differential pair)
Jitter Attenuated Clock
Table 1-9
Table 1-9: Clock Source to FPGA U1 Connections
Clock Source Pin
26
Send Feedback
1-8).
Clock Name Reference
U6
U45
J11
J12
J16
J15
U70
lists the pin-to-pin connections from each clock source to the FPGA.
Schematic Net Name
U6.5 SYSCLK_N
U6.4 SYSCLK_P
U45.5 USER_CLOCK_N
U45.4 USER_CLOCK_P
J12.1 USER_SMA_CLOCK_N
J11.1 USER_SMA_CLOCK_P
J15.1 SMA_MGT_REFCLK_N
J16.1 SMA_MGT_REFCLK_P
U70.29 Si5326_OUT_N
U70.28 Si5326_OUT_P
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Description
SiT9102 2.5V LVDS 200 MHz Fixed Frequency
Oscillator (Si Time). See System Clock Source, page
2
Si570 3.3V LVDS I C Programmable Oscillator
(Silicon Labs). Default power-on frequency 156.250
MHz. See Programmable User Clock Source, page
USER_SMA_CLOCK_P (net name).
See User SMA Clock Input, page
USER_SMA_CLOCK_N (net name)
See User SMA Clock Input, page 28
SMA_MGT_REFCLK_P (net name).
See GTX SMA Clock Input, page
SMA_MGT_REFCLK_N (net name).
See GTX SMA Clock Input, page
Si5324C LVDS precision clock multiplier/jitter
attenuator (Silicon Labs).
See Jitter Attenuated Clock, page
I/O Standard
LVDS
LVDS
LVDS_25
LVDS_25
LVDS_25
LVDS_25
N/A (MGT REFCLK INPUT)
N/A (MGT REFCLK INPUT)
N/A (MGT REFCLK INPUT)
N/A (MGT REFCLK INPUT)
UG810 (v1.6.2) August 26, 2015
27.
27.
28.
29.
29.
29.
U1 FPGA Pin
AD11
AD12
K29
K28
K25
L25
J7
J8
L7
L8
KC705 Evaluation Board