Configuration Options - Xilinx KC705 User Manual

Configuration Options

The FPGA on the KC705 board can be configured by the following methods:
•
•
•
See 7 Series FPGAs Configuration User Guide (UG470)
modes.
The method used to configure the FPGA is controlled by the mode pin (M2, M1, M0)
settings selected through DIP switch SW13.
settings.
Table 1-35: Mode Switch SW13 Settings
Master SPI
Master BPI
JTAG
Figure 1-39
X-Ref Target - Figure 1-39
The mode pins settings on SW13 determine if the Linear BPI or the Quad SPI flash memory
is used for configuring the FPGA. DIP switch SW13 also provides the upper two address
bits for the Linear BPI flash memory and can be used to select one of multiple stored
configuration bitstreams.
nonvolatile flash devices used for configuration and the FPGA.
KC705 Evaluation Board
UG810 (v1.6.2) August 26, 2015
Master BPI (uses the Linear BPI flash memory)
Master SPI (uses the Quad SPI flash memory)
JTAG (uses the USB-to-JTAG Bridge or Download cable). See
page 24 for more information
Configuration Mode
shows mode switch SW13.
FLASH_A25
FLASH_A24
FPGA_M2
FPGA_M1
FPGA_M0
R396
1.21kΩ
0.1 W
1%
R397
1.21kΩ
0.1 W
1%
GND
Figure 1-40
www.xilinx.com
[Ref 2]
Table 1-35 lists the supported mode switch
Mode Pins (M[2:0])
001
010
101
SW13
ON
10
9
8
7
6
SDA05H1SBD
R398 R400
1.21kΩ 1.21kΩ
0.1 W 0.1 W
1% 1%
R399
1.21kΩ
0.1 W
1%
Figure 1-39: Mode Switch
shows the connectivity between the onboard
Configuration Options
USB JTAG Module,
for details on configuration
Bus Width CCLK Direction
x1, x2, x4 Output
x8, x16 Output
x1 Not Applicable
VCC2V5
R401 R402
220Ω 220Ω
0.1 W 0.1 W
1% 1%
1
2
3
4
5
UG810_c1_39_031214
Send Feedback
73