Xilinx KC705 User Manual page 17

Table 1-4: DDR3 Memory Connections to the FPGA (Cont'd)
KC705 Evaluation Board
UG810 (v1.6.2) August 26, 2015
U1 FPGA Pin Net Name
AB17 DDR3_DM1
AF17 DDR3_DM2
AE16 DDR3_DM3
AK5 DDR3_DM4
AJ3 DDR3_DM5
AF6 DDR3_DM6
AC7 DDR3_DM7
AC15 DDR3_DQS0_N
AC16 DDR3_DQS0_P
Y18 DDR3_DQS1_N
Y19 DDR3_DQS1_P
AK18 DDR3_DQS2_N
AJ18 DDR3_DQS2_P
AJ16 DDR3_DQS3_N
AH16 DDR3_DQS3_P
AJ7 DDR3_DQS4_N
AH7 DDR3_DQS4_P
AH1 DDR3_DQS5_N
AG2 DDR3_DQS5_P
AG3 DDR3_DQS6_N
AG4 DDR3_DQS6_P
AD1 DDR3_DQS7_N
AD2 DDR3_DQS7_P
AD8 DDR3_ODT0
AC10 DDR3_ODT1
AK3 DDR3_RESET_B
AC12 DDR3_S0_B
AE8 DDR3_S1_B
DDR3_TEMP_E
AJ9
VENT
AE9 DDR3_WE_B
AC11 DDR3_CAS_B
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J1 DDR3 Memory
I/O Standard
Pin Number
SSTL15 28
SSTL15 46
SSTL15 63
SSTL15 136
SSTL15 153
SSTL15 170
SSTL15 187
DIFF_SSTL15 10
DIFF_SSTL15 12
DIFF_SSTL15 27
DIFF_SSTL15 29
DIFF_SSTL15 45
DIFF_SSTL15 47
DIFF_SSTL15 62
DIFF_SSTL15 64
DIFF_SSTL15 135
DIFF_SSTL15 137
DIFF_SSTL15 152
DIFF_SSTL15 154
DIFF_SSTL15 169
DIFF_SSTL15 171
DIFF_SSTL15 186
DIFF_SSTL15 188
SSTL15 116
SSTL15 120
LVCMOS15 30
SSTL15 114
SSTL15 121
SSTL15 198
SSTL15 113
SSTL15 115
Feature Descriptions
Pin Name
DM1
DM2
DM3
DM4
DM5
DM6
DM7
DQS0_N
DQS0_P
DQS1_N
DQS1_P
DQS2_N
DQS2_P
DQS3_N
DQS3_P
DQS4_N
DQS4_P
DQS5_N
DQS5_P
DQS6_N
DQS6_P
DQS7_N
DQS7_P
ODT0
ODT1
RESET_B
S0_B
S1_B
EVENT_B
WE_B
CAS_B
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