Xilinx KC705 User Manual page 29

no external parallel termination resistor). The user-provided 2.5V differential clock circuit
is shown in
X-Ref Target - Figure 1-12
GTX SMA Clock Input
[Figure
The KC705 board includes a pair of SMA connectors for a GTX clock wired to GTX Quad
bank 117. This differential clock has signal names SMA_MGT_REFCLK_P and
SMA_REFCLK_N, which are connected to FPGA U1 pins J8 and J7 respectively.
Figure 1-13
•
•
X-Ref Target - Figure 1-13
Jitter Attenuated Clock
[Figure
The KC705 board includes a Silicon Labs Si5324 jitter attenuator U70 on the back side of the
board. FPGA user logic can implement a clock recovery circuit and then output this clock
to a differential I/O pair on I/O bank 13 (REC_CLOCK_C_P, FPGA U1 pin W27 and
REC_CLOCK_C_N, FPGA U1 pin W28) for jitter attenuation. The jitter attenuated clock
(SI5326_OUT_C_P, SI5326_OUT_C_N) is then routed as a reference clock to GTX Quad 116
inputs MGTREFCLK0P (FPGA U1 pin L8) and MGTREFCLK0N (FPGA U1 pin L7).
KC705 Evaluation Board
UG810 (v1.6.2) August 26, 2015
Figure 1-12.
SMA
Connector
SMA
Connector
Figure 1-12: User SMA Clock Source
1-2, callout 10]
shows this AC-coupled clock circuit.
External user-provided GTX reference clock on SMA input connectors
Differential Input
J16
SMA_MGT_REFCLK_C_P
SMA
Connector
J15
GND
SMA_MGT_REFCLK_C_N
SMA
Connector
GND
Figure 1-13: GTX SMA Clock Source
1-2, callout 11]
www.xilinx.com
J11
USER_SMA_CLOCK_P
GND
J12
USER_SMA_CLOCK_N
GND
UG810_c1_12_031214
C11
SMA_MGT_REFCLK_P
0.01 μF 25V
X7R
C10
SMA_MGT_REFCLK_N
0.01 μF 25V
X7R
Feature Descriptions
UG810_c1_13_031214
29
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