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Xilinx KCU1250 User Manual

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KCU1250 Board
User Guide
UG1057 (v1.0) December 19, 2014

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Summary of Contents for Xilinx KCU1250

  • Page 1 KCU1250 Board User Guide UG1057 (v1.0) December 19, 2014...

  • Page 2: Revision History

    Revision History The following table shows the revision history for this document. Date Version Revision 12/19/2014 Initial Xilinx release. KCU1250 User Guide www.xilinx.com UG1057 (v1.0) December 19, 2014...

  • Page 3: Table Of Contents

    KCU1250 Board XDC Listing........
  • Page 4 Xilinx Resources ........

  • Page 5: Chapter 1: Kcu1250 Board Features And Operation

    KCU1250 Board Features and Operation Introduction This user guide describes the components, features, and operation of the KCU1250 UltraScale™ FPGA GTH transceiver characterization board. The KCU1250 board provides the hardware environment for characterizing and evaluating the GTH transceivers on an UltraScale XCKU040-2FFVA1156E FPGA.
  • Page 6 I2C bus • PMBus connectivity to the boards digital power supplies • Active cooling for the FPGA The KCU1250 board block diagram is shown in Figure 1-1. X-Ref Target - Figure 1-1 Figure 1-1: KCU1250 Board Block Diagram KCU1250 User Guide www.xilinx.com...
  • Page 7 Table 1-1 and in subsequent sections. The KCU1250 board can be damaged by electrostatic discharge (ESD). Follow standard ESD CAUTION! prevention measures when handling the board Do not remove the rubber feet from the board. The feet provide clearance to prevent short...
  • Page 8 Chapter 1: KCU1250 Board Features and Operation Table 1-1 describes the callouts in Figure 1-2. Table 1-1: KCU1250 Board Features and Operation Figure Reference Designator Feature Description Callout UltraScale XCKU040-2FFVA1156E FPGA, page 18 Power switch, page 10 12V mini-fit connector,...

  • Page 9: Power Management

    Figure 1-2) using the 12V AC adapter included with the KCU1250 board characterization kit. J28 is a 6-pin (2 x 3), right angle, mini-fit connector. When supplying 12V through J28, use only the power supply provided for use with this CAUTION! board (Xilinx part number 3800033).
  • Page 10 Power Switch The KCU1250 board main power is turned on or off using the SW1 switch (callout 2, Figure 1-2). When the switch is in the on position, power is applied to the board and the...
  • Page 11 Chapter 1: KCU1250 Board Features and Operation X-Ref Target - Figure 1-3 Figure 1-3: KCU1250 Board Power Supply Block Diagram KCU1250 User Guide www.xilinx.com Send Feedback UG1057 (v1.0) December 19, 2014...
  • Page 12 Chapter 1: KCU1250 Board Features and Operation The KCU1250 board uses power regulators and PMBus compliant digital PWM system controllers from Maxim Integrated to supply the FPGA logic and utilities voltages listed in Table 1-2. The board can also be configured to use an external bench power supply for each voltage.
  • Page 13 Chapter 1: KCU1250 Board Features and Operation Using External Power Sources Each power rail for the FPGA logic and MGT transceivers has an associated Euro-Mag spring-clamp terminal block (callout 18, Figure 1-2), which can be used to provide power from an external source (Table 1-3).
  • Page 14 KCU1250 system controller or via the Maxim PowerTool™ software graphical user interface. The KCU1250 system controller is the simplest and most convenient way to monitor the voltage and current values for the power rails listed in Table 1-3.
  • Page 15 Chapter 1: KCU1250 Board Features and Operation More information about the power system components used on the KCU1250 board is available from the Maxim Integrated InTune digital power website [Ref MGT Transceiver Power Module The KCU1250 board includes one MGT transceiver power module (callout 19, Figure 1-2).
  • Page 16 Chapter 1: KCU1250 Board Features and Operation Active Heatsink Power Connector An active heat sink (Figure 1-6) is provided for the FPGA (callout 23, Figure 1-2). A 12V fan is affixed to the heat sink and is powered from the 3-pin friction lock header J99 (Figure 1-7).
  • Page 17 Chapter 1: KCU1250 Board Features and Operation The fan power connections are detailed in Table 1-6: Table 1-5: Fan Power Connections Fan Wire Header Pin Black J99.1 - GND J99.2 - 12V Blue J99.3 - NC Figure 1-7 shows the heat sink fan power connector J99.

  • Page 18: Ultrascale Fpga

    Chapter 1: KCU1250 Board Features and Operation UltraScale FPGA The KCU1250 board is populated with the UltraScale XCKU040-2FFVA1156E FPGA at U1 (callout 1, Figure 1-2). For further information on UltraScale FPGAs, see UltraScale Architecture and Product Overview (DS890) [Ref FPGA Configuration The FPGA is configured though one of these options: •...
  • Page 19 Chapter 1: KCU1250 Board Features and Operation The JTAG chain of the KCU1250 board is shown in Figure 1-8. By default, only the UltraScale FPGA is part of the chain (J6 jumper uninstalled). Installing the J6 jumper enables an 8-bit bus transceiver (U69, SN74AVC8T245) and adds the FMC interfaces to the chain.

  • Page 20: System Controller

    During FPGA initialization, the INIT LED illuminates RED. When FPGA initialization has completed, the LED illuminates GREEN. System Controller The KCU1250 board utilizes a Xilinx XC7Z010-CLG225 Zynq-7000 AP SoC U38 (callout 33, Figure D-1) system controller that can be used to: •...
  • Page 21 Chapter 1: KCU1250 Board Features and Operation System Controller Configuration DIP Switches The DIP switch SW13 (callout 8, Figure 1-2) shown in Figure 1-9 selects the address of the UltraScale FPGA configuration bitstream to be loaded from the SD card. The switch ON position is indicated by the arrow next to bit 1 of the switch.

  • Page 22: Usb To Dual-Uart Bridge

    USB to Dual-UART Bridge The KCU1250 board uses a single-chip USB to dual-UART bridge (U32, Silicon Laboratories CP2105) for simultaneous serial communication between a host terminal and the UltraScale FPGA, and between a host terminal and the Zynq-7000 AP SoC system controller. The...

  • Page 23: 300 Mhz Lvds Oscillator

    The second port of the CP2105 USB to dual-UART is connected to the onboard system controller. See Appendix D, System Controller. 300 MHz LVDS Oscillator The KCU1250 board has one 300 MHz LVDS oscillator U42 (callout 11, Figure 1-2) connected to multi-region clock capable (MRCC) inputs on the FPGA. Table 1-9 lists the FPGA pin connections to the LVDS oscillator.

  • Page 24: Differential Sma Mrcc Pin Inputs

    Chapter 1: KCU1250 Board Features and Operation Differential SMA MRCC Pin Inputs The KCU1250 board provides two pairs of differential SMA transceiver clock inputs (callout Figure 1-2) that can be used for connecting to an external clock source. The FPGA MRCC...

  • Page 25: User Leds (Active-High)

    Chapter 1: KCU1250 Board Features and Operation Table 1-11: SuperClock-2 FPGA I/O Mapping (Cont’d) FPGA(U1) J36 Pin Schematic Net Name Function Direction IOSTANDARD Function Direction AP20 Control I/O Output LVCMOS18 CM_H_INT_ALRM INT_ALRM Input AP21 Control I/O Output LVCMOS18 CM_C1B Input...

  • Page 26: User Dip Switches (Active-High) And I/O Header

    Chapter 1: KCU1250 Board Features and Operation User DIP Switches (Active-High) and I/O Header The DIP switch SW3 (callout 26, Figure 1-2) provides a set of eight active-High switches which connect to user I/O pins on the FPGA, as shown in Table 1-13.

  • Page 27: User Push Buttons (Active-High)

    Chapter 1: KCU1250 Board Features and Operation Figure 1-11 shows the user I/O connector J28 (callout 28, Figure 1-2). X-Ref Target - Figure 1-11 Figure 1-11: User I/O (J95) User Push Buttons (Active-High) SW8 and SW9 (callout 25, Figure 1-2) are active-High user push buttons that are connected...

  • Page 28: Mgt Transceivers And Reference Clocks

    Chapter 1: KCU1250 Board Features and Operation MGT Transceivers and Reference Clocks The KCU1250 board provides access to all GTH transceiver and reference clock pins of the XCKU040 FPGA, as shown in Figure 1-12. The MGT transceivers are grouped into five sets of four RX-TX lanes, referred to as a quad (Q224 - Q228).
  • Page 29 Chapter 1: KCU1250 Board Features and Operation Each MGT quad and its associated reference clocks (CLK0 and CLK1) are brought out to a connector pad, which interfaces with Samtec BullsEye connectors used with the Samtec HDR-155805-01-BEYE cable assembly. Contact Samtec, Inc., for information about this or...
  • Page 30 Chapter 1: KCU1250 Board Features and Operation Table 1-15: GTH Transceiver Pins (Cont’d) U1 FPGA Pin Net Name Quad Connector Trace Length (mils) 131_TX2_P 3061.0 131_TX3_N 2769.0 131_TX3_P 2769.6 132_RX0_N 2443.3 132_RX0_P 2442.5 132_RX1_N 3183.3 132_RX1_P 3182.3 132_RX2_N 3030.5 132_RX2_P 3031.3...
  • Page 31 Chapter 1: KCU1250 Board Features and Operation Table 1-15: GTH Transceiver Pins (Cont’d) U1 FPGA Pin Net Name Quad Connector Trace Length (mils) 225_RX0_N 3027.1 225_RX0_P 3027.7 225_RX1_N 2419.3 225_RX1_P 2419.9 225_RX2_N 2340.7 225_RX2_P 2339.8 225_RX3_N 2889.8 225_RX3_P 2888.8 225_TX0_N 2917.7...
  • Page 32 Chapter 1: KCU1250 Board Features and Operation Table 1-15: GTH Transceiver Pins (Cont’d) U1 FPGA Pin Net Name Quad Connector Trace Length (mils) 227_RX1_P 2288.5 227_RX2_N 2368.0 227_RX2_P 2367.0 227_RX3_N 2995.4 227_RX3_P 2994.4 227_TX0_N 2802.3 227_TX0_P 2803.0 227_TX1_N 2568.8 227_TX1_P 2569.5...
  • Page 33 Chapter 1: KCU1250 Board Features and Operation The information for each GTH transceiver clock input is shown in Table 1-16. Table 1-16: GTH Transceiver Reference Clock Inputs U1 FPGA Pin Net Name Quad Connector 131_REFCLK0_N 131_REFCLK0_P 131_REFCLK1_N 131_REFCLK1_P 132_REFCLK0_N 132_REFCLK0_P...

  • Page 34: Fpga Mezzanine Card Hpc Interface

    Chapter 1: KCU1250 Board Features and Operation FPGA Mezzanine Card HPC Interface The KCU1250 board features three high pin count (HPC) connectors as defined by the VITA 57.1 FMC specification (callout 28, 29 and 30, Figure 1-2). The FMC HPC connector is a 10 x 40 position socket.
  • Page 35 Chapter 1: KCU1250 Board Features and Operation The FMC HPC connectors on the KCU1250 board are identified as FMC1 at JA2, FMC2 at JA3, and FMC3 at JA4. The connections for each of these connectors are listed in Table 1-17,...
  • Page 36 Chapter 1: KCU1250 Board Features and Operation Table 1-17: VITA 57.1 FMC1 HPC Connections at JA2 (Cont’d) U1 FPGA Pin Net Name FMC Pin FMC1_LA03P FMC1_LA03N FMC1_LA04P FMC1_LA04N FMC1_LA05P FMC1_LA05N FMC1_LA06P FMC1_LA06N FMC1_LA07P FMC1_LA07N FMC1_LA08P FMC1_LA08N FMC1_LA09P FMC1_LA09N FMC1_LA10P FMC1_LA10N...
  • Page 37 Chapter 1: KCU1250 Board Features and Operation Table 1-17: VITA 57.1 FMC1 HPC Connections at JA2 (Cont’d) U1 FPGA Pin Net Name FMC Pin FMC1_LA20N FMC1_LA21P FMC1_LA21N FMC1_LA22P FMC1_LA22N FMC1_LA23P FMC1_LA23N FMC1_LA24P FMC1_LA24N FMC1_LA25P FMC1_LA25N FMC1_LA26P FMC1_LA26N FMC1_LA27P FMC1_LA27N FMC1_LA28P...
  • Page 38 Chapter 1: KCU1250 Board Features and Operation Table 1-18 shows the VITA 57.1 FMC2 HPC connections at JA3. Table 1-18: VITA 57.1 FMC2 HPC Connections at JA3 U1 FPGA Pin Net Name FMC Pin FMC2_CLK0_M2C_P FMC2_CLK0_M2C_N FMC2_CLK1_M2C_P FMC2_CLK1_M2C_N AU17 FMC2_HA00_CC_P...
  • Page 39 Chapter 1: KCU1250 Board Features and Operation Table 1-18: VITA 57.1 FMC2 HPC Connections at JA3 U1 FPGA Pin Net Name FMC Pin FMC2_LA04N AK10 FMC2_LA05P FMC2_LA05N FMC2_LA06P FMC2_LA06N AL10 FMC2_LA07P AM10 FMC2_LA07N FMC2_LA08P FMC2_LA08N FMC2_LA09P FMC2_LA09N AD10 FMC2_LA10P AE10...
  • Page 40 Chapter 1: KCU1250 Board Features and Operation Table 1-18: VITA 57.1 FMC2 HPC Connections at JA3 U1 FPGA Pin Net Name FMC Pin FMC2_LA22P FMC2_LA22N FMC2_LA23P FMC2_LA23N FMC2_LA24P FMC2_LA24N FMC2_LA25P FMC2_LA25N FMC2_LA26P FMC2_LA26N FMC2_LA27P FMC2_LA27N FMC2_LA28P FMC2_LA28N FMC2_LA29P FMC2_LA29N FMC2_LA30P...
  • Page 41 Chapter 1: KCU1250 Board Features and Operation Table 1-19 shows the VITA 57.1 FMC3 HPC connections at JA4. Table 1-19: VITA 57.1 FMC3 HPC Connections at JA4 U1 FPGA Pin Net Name FMC Pin FMC3_CLK0_M2C_P FMC3_CLK0_M2C_N AB30 FMC3_CLK1_M2C_P AB31 FMC3_CLK1_M2C_N...
  • Page 42 Chapter 1: KCU1250 Board Features and Operation Table 1-19: VITA 57.1 FMC3 HPC Connections at JA4 (Cont’d) U1 FPGA Pin Net Name FMC Pin FMC3_LA03N FMC3_LA04P FMC3_LA04N FMC3_LA05P FMC3_LA05N FMC3_LA06P FMC3_LA06N FMC3_LA07P FMC3_LA07N FMC3_LA08P FMC3_LA08N FMC3_LA09P FMC3_LA09N FMC3_LA10P FMC3_LA10N FMC3_LA11P...
  • Page 43 Chapter 1: KCU1250 Board Features and Operation Table 1-19: VITA 57.1 FMC3 HPC Connections at JA4 (Cont’d) U1 FPGA Pin Net Name FMC Pin FMC3_LA21P FMC3_LA21N FMC3_LA22P FMC3_LA22N FMC3_LA23P FMC3_LA23N AC33 FMC3_LA24P AD33 FMC3_LA24N AA34 FMC3_LA25P AB34 FMC3_LA25N AA29 FMC3_LA26P...

  • Page 44: System Monitor

    Chapter 1: KCU1250 Board Features and Operation System Monitor The SYSMON monitors the physical environment using on-chip temperature and supply sensors, up to 17 external analog inputs, and an integrated analog-to-digital converter (ADC). The SYSMON is powered using the on-chip reference voltage (VREFP) shown in Figure 1-14.

  • Page 45: I2C Bus Management

    Chapter 1: KCU1250 Board Features and Operation I2C Bus Management The I2C bus is routed through U22, an 8-channel I2C-bus multiplexer (NXP Semiconductor TCA9548). The I2C IDcode for the TCA9548 device is 0x75. The multiplexer provides I2C/PMBus communication between the bus master (system controller or FPGA) and six sub-systems: •...
  • Page 46 Chapter 1: KCU1250 Board Features and Operation X-Ref Target - Figure 1-15 Figure 1-15: I2C Bus Multiplexer and Upstream Repeater KCU1250 User Guide www.xilinx.com Send Feedback UG1057 (v1.0) December 19, 2014...

  • Page 47: Appendix A: Default Jumper Settings

    Appendix A Default Jumper Settings Introduction Table A-1 lists the jumpers that must be installed on the KCU1250 board for proper operation. These jumpers must be installed except where specifically noted in this user guide. Any jumper not listed in Table A-1 should be left open for normal operation.

  • Page 48: Appendix B: Vita 57.1 Fmc Connector Pinouts

    Introduction Figure B-1 provides a cross-reference of signal names to pin coordinates for the VITA 57.1 FMC HPC connector. X-Ref Target - Figure B-1 Figure B-1: FMC Connector Pinouts KCU1250 User Guide www.xilinx.com Send Feedback UG1057 (v1.0) December 19, 2014...

  • Page 49: Appendix C: Master Constraints File Listing

    The KCU1250 board master Xilinx design constraints (XDC) file template provides for designs targeting the KCU1250 UltraScale FPGA GTH transceiver characterization board. Net names in the listed constraints correlate with net names on the KCU1250 board schematic. Users must identify the appropriate pins and replace the net names with net names in the user RTL.
  • Page 50 IOSTANDARD LVCMOS18 [get_ports "FMC1_LA16P"] set_property PACKAGE_PIN A10 [get_ports "FMC1_LA16N"] set_property IOSTANDARD LVCMOS18 [get_ports "FMC1_LA16N"] set_property PACKAGE_PIN D23 [get_ports "FMC1_LA17_CC_P"] set_property IOSTANDARD LVCMOS18 [get_ports "FMC1_LA17_CC_P"] set_property PACKAGE_PIN C23 [get_ports "FMC1_LA17_CC_N"] KCU1250 User Guide www.xilinx.com Send Feedback UG1057 (v1.0) December 19, 2014...
  • Page 51 PACKAGE_PIN E26 [get_ports "FMC1_LA31P"] set_property IOSTANDARD LVCMOS18 [get_ports "FMC1_LA31P"] set_property PACKAGE_PIN D26 [get_ports "FMC1_LA31N"] set_property IOSTANDARD LVCMOS18 [get_ports "FMC1_LA31N"] set_property PACKAGE_PIN A27 [get_ports "FMC1_LA32P"] set_property IOSTANDARD LVCMOS18 [get_ports "FMC1_LA32P"] KCU1250 User Guide www.xilinx.com Send Feedback UG1057 (v1.0) December 19, 2014...
  • Page 52 PACKAGE_PIN AG9 [get_ports "FMC2_CLK0_M2C_N"] set_property IOSTANDARD LVCMOS18 [get_ports "FMC2_CLK0_M2C_N"] set_property PACKAGE_PIN P24 [get_ports "FMC2_CLK1_M2C_P"] set_property IOSTANDARD LVCMOS18 [get_ports "FMC2_CLK1_M2C_P"] set_property PACKAGE_PIN P25 [get_ports "FMC2_CLK1_M2C_N"] set_property IOSTANDARD LVCMOS18 [get_ports "FMC2_CLK1_M2C_N"] KCU1250 User Guide www.xilinx.com Send Feedback UG1057 (v1.0) December 19, 2014...
  • Page 53 PACKAGE_PIN AE12 [get_ports "FMC2_LA13P"] set_property IOSTANDARD LVCMOS18 [get_ports "FMC2_LA13P"] set_property PACKAGE_PIN AF12 [get_ports "FMC2_LA13N"] set_property IOSTANDARD LVCMOS18 [get_ports "FMC2_LA13N"] set_property PACKAGE_PIN AH13 [get_ports "FMC2_LA14P"] set_property IOSTANDARD LVCMOS18 [get_ports "FMC2_LA14P"] KCU1250 User Guide www.xilinx.com Send Feedback UG1057 (v1.0) December 19, 2014...
  • Page 54 IOSTANDARD LVCMOS18 [get_ports "FMC2_LA27N"] set_property PACKAGE_PIN L25 [get_ports "FMC2_LA28P"] set_property IOSTANDARD LVCMOS18 [get_ports "FMC2_LA28P"] set_property PACKAGE_PIN K25 [get_ports "FMC2_LA28N"] set_property IOSTANDARD LVCMOS18 [get_ports "FMC2_LA28N"] set_property PACKAGE_PIN L23 [get_ports "FMC2_LA29P"] KCU1250 User Guide www.xilinx.com Send Feedback UG1057 (v1.0) December 19, 2014...
  • Page 55 PACKAGE_PIN G25 [get_ports "FMC2_HA08P"] set_property IOSTANDARD LVCMOS18 [get_ports "FMC2_HA08P"] set_property PACKAGE_PIN G26 [get_ports "FMC2_HA08N"] set_property IOSTANDARD LVCMOS18 [get_ports "FMC2_HA08N"] set_property PACKAGE_PIN H27 [get_ports "FMC2_HA09P"] set_property IOSTANDARD LVCMOS18 [get_ports "FMC2_HA09P"] KCU1250 User Guide www.xilinx.com Send Feedback UG1057 (v1.0) December 19, 2014...
  • Page 56 IOSTANDARD LVCMOS18 [get_ports "FMC3_LA09P"] set_property PACKAGE_PIN T23 [get_ports "FMC3_LA09N"] set_property IOSTANDARD LVCMOS18 [get_ports "FMC3_LA09N"] set_property PACKAGE_PIN V22 [get_ports "FMC3_LA10P"] set_property IOSTANDARD LVCMOS18 [get_ports "FMC3_LA10P"] set_property PACKAGE_PIN V23 [get_ports "FMC3_LA10N"] KCU1250 User Guide www.xilinx.com Send Feedback UG1057 (v1.0) December 19, 2014...
  • Page 57 PACKAGE_PIN AC33 [get_ports "FMC3_LA24P"] set_property IOSTANDARD LVCMOS18 [get_ports "FMC3_LA24P"] set_property PACKAGE_PIN AD33 [get_ports "FMC3_LA24N"] set_property IOSTANDARD LVCMOS18 [get_ports "FMC3_LA24N"] set_property PACKAGE_PIN AA34 [get_ports "FMC3_LA25P"] set_property IOSTANDARD LVCMOS18 [get_ports "FMC3_LA25P"] KCU1250 User Guide www.xilinx.com Send Feedback UG1057 (v1.0) December 19, 2014...
  • Page 58 IOSTANDARD LVCMOS18 [get_ports "FMC3_HA04P"] set_property PACKAGE_PIN AC24 [get_ports "FMC3_HA04N"] set_property IOSTANDARD LVCMOS18 [get_ports "FMC3_HA04N"] set_property PACKAGE_PIN AD25 [get_ports "FMC3_HA05P"] set_property IOSTANDARD LVCMOS18 [get_ports "FMC3_HA05P"] set_property PACKAGE_PIN AD26 [get_ports "FMC3_HA05N"] KCU1250 User Guide www.xilinx.com Send Feedback UG1057 (v1.0) December 19, 2014...
  • Page 59 PACKAGE_PIN J8 [get_ports "CM_LVDS2_P"] set_property IOSTANDARD LVCMOS18 [get_ports "CM_LVDS2_P"] set_property PACKAGE_PIN H8 [get_ports "CM_LVDS2_N"] set_property IOSTANDARD LVCMOS18 [get_ports "CM_LVDS2_N"] set_property PACKAGE_PIN AK22 [get_ports "CM_GCLK_P"] set_property IOSTANDARD LVCMOS18 [get_ports "CM_GCLK_P"] KCU1250 User Guide www.xilinx.com Send Feedback UG1057 (v1.0) December 19, 2014...
  • Page 60 [get_ports "CLK_DIFF_2_N"] set_property IOSTANDARD LVDS [get_ports "CLK_DIFF_2_N"] #SYSTEM CLOCKS set_property PACKAGE_PIN E18 [get_ports "LVDS_OSC_P"] set_property IOSTANDARD LVDS [get_ports "LVDS_OSC_P"] set_property PACKAGE_PIN E17 [get_ports "LVDS_OSC_N"] set_property IOSTANDARD LVDS [get_ports "LVDS_OSC_N"] KCU1250 User Guide www.xilinx.com Send Feedback UG1057 (v1.0) December 19, 2014...
  • Page 61 PACKAGE_PIN J33 [get_ports "131_RX3_P"] set_property PACKAGE_PIN J34 [get_ports "131_RX3_N"] set_property PACKAGE_PIN M31 [get_ports "131_TX2_P"] set_property PACKAGE_PIN M32 [get_ports "131_TX2_N"] set_property PACKAGE_PIN L33 [get_ports "131_RX2_P"] set_property PACKAGE_PIN L34 [get_ports "131_RX2_N"] KCU1250 User Guide www.xilinx.com Send Feedback UG1057 (v1.0) December 19, 2014...
  • Page 62 PACKAGE_PIN AC3 [get_ports "225_TX3_N"] set_property PACKAGE_PIN AB2 [get_ports "225_RX3_P"] set_property PACKAGE_PIN AB1 [get_ports "225_RX3_N"] set_property PACKAGE_PIN AE4 [get_ports "225_TX2_P"] set_property PACKAGE_PIN AE3 [get_ports "225_TX2_N"] set_property PACKAGE_PIN AD2 [get_ports "225_RX2_P"] KCU1250 User Guide www.xilinx.com Send Feedback UG1057 (v1.0) December 19, 2014...
  • Page 63 PACKAGE_PIN B6 [get_ports "228_TX3_P"] set_property PACKAGE_PIN B5 [get_ports "228_TX3_N"] set_property PACKAGE_PIN A4 [get_ports "228_RX3_P"] set_property PACKAGE_PIN A3 [get_ports "228_RX3_N"] set_property PACKAGE_PIN C4 [get_ports "228_TX2_P"] set_property PACKAGE_PIN C3 [get_ports "228_TX2_N"] KCU1250 User Guide www.xilinx.com Send Feedback UG1057 (v1.0) December 19, 2014...
  • Page 64 PACKAGE_PIN D2 [get_ports "228_RX1_P"] set_property PACKAGE_PIN D1 [get_ports "228_RX1_N"] set_property PACKAGE_PIN F6 [get_ports "228_TX0_P"] set_property PACKAGE_PIN F5 [get_ports "228_TX0_N"] set_property PACKAGE_PIN E4 [get_ports "228_RX0_P"] set_property PACKAGE_PIN E3 [get_ports "228_RX0_N"] KCU1250 User Guide www.xilinx.com Send Feedback UG1057 (v1.0) December 19, 2014...

  • Page 65: Appendix D: System Controller

    USB to Dual-UART Bridge. X-Ref Target - Figure D-1 Figure D-1: Silicon Labs Enhanced COM Port The main menu lists the available options. KCU1250 System Controller - Main Menu - ----------------------------- 1. Set Programmable Clocks 2. Get Power System (PMBUS) Voltages 3.
  • Page 66 Module) clock sources. KCU1250 System Controller - Clock Menu - ----------------------------- 1. Set KCU1250 Si570 Frequency 2. Set KCU1250 Si5368 Frequency 0. Return to Main Menu Clock Menu Options This section includes a description of the clock menu options, presenting arbitrary sample value entries and the system controller responses.
  • Page 67 This option returns to the menu level above. PMBus Menu The PMBus bus commands are used to read the voltage settings of the KCU1250 board power rails controlled by the Maxim power system. Through the PMBus menu these power rails can be read once or scanned continuously until stopped by a key press.
  • Page 68 Appendix D: System Controller PMBus Menu Options KCU1250 System Controller - PMBus Menu - ----------------------------- 1. Get PMBus Voltages 2. Continuous Scan PMBus Voltages 3. Get VCCINT Voltage 4. Get VCCAUX Voltage 5. Get VCCBRAM Voltage 6. Get VCCOHP Voltage 7.
  • Page 69 Unscaled Hex: MSB = 0x34, LSB = 0xC8 (The returned values include diagnostic information.) • Get UTIL2V5 Voltage UTIL2V5 = 2.500V Unscaled Hex: MSB = 0x28, LSB = 0x02 (The returned values include diagnostic information.) KCU1250 User Guide www.xilinx.com Send Feedback UG1057 (v1.0) December 19, 2014...
  • Page 70 Appendix D: System Controller Power Monitoring Data Menu The KCU1250 board includes the Texas Instruments INA226 power monitoring device. The Power Monitoring Data menu, unlike the PMBus menu, provides both voltage and current monitoring for the MGT power modules, as well as for the FPGA fabric power rails.
  • Page 71 0. Return to Previous Menu FPGA Mezzanine Card Menu The KCU1250 board includes three FPGA mezzanine card (FMC) ANSI/VITA 57.1 expansion interfaces. All FMC cards must host an IIC EEPROM that can be read through the FMC menu. A raw hexadecimal display and a formatted version of the FMC EEPROM data are provided through the FMC menu.
  • Page 72 Appendix D: System Controller These mezzanine cards can be attached to JA2 (callout 28), J3A (callout 29), or J4A (callout 30) of the KCU1250 board expansion ports. Table D-2 shows the accessible clock resources on each FMC module. Table D-2: Clock Resources on FMC Modules...
  • Page 73 - DC Output Records (three groups) If the FMC IIC EEPROM has not been programmed, ReadBuffer[000] - ReadBuffer[255] displays buffer contents = 0xFF, and the common header reports "Invalid Format Version FF". KCU1250 User Guide www.xilinx.com Send Feedback UG1057 (v1.0) December 19, 2014...
  • Page 74 2. Continuous Scan GPIO Readings 0. Return to Main Menu Select an option • Get GPIO PL Data The signals monitored with this option are currently not available in the KCU1250 board. ---------------------- FMC1_PRSNT = NO FMC2_PRSNT = NO PMBUS_CABLE_B = NO...
  • Page 75 FPGA from an SD card (callout 7). The directory structure and content of the SD card must adhere to the data format specified in Xilinx XAPP1229. One of 16 bitstreams can be selected for use by the configuration engine by setting a binary encoded value on the...

  • Page 76: Appendix F: Regulatory And Compliance Information

    This product is designed and tested to conform to the European Union directives and standards described in this section. Refer to the KCU1250 board master answer record concerning the CE requirements for the PC Test Environment: Master Answer Record (Xilinx AR63058) Declaration of Conformity The Kintex UltraScale KCU1250 Declaration of Conformity will be made available online.

  • Page 77: Markings

    This product complies with Directive 2002/95/EC on the restriction of hazardous substances (RoHS) in electrical and electronic equipment. This product complies with CE Directives 2006/95/EC, Low Voltage Directive (LVD) and 2004/108/EC, Electromagnetic Compatibility (EMC) Directive. KCU1250 User Guide www.xilinx.com Send Feedback UG1057 (v1.0) December 19, 2014...

  • Page 78: Appendix F: Additional Resources And Legal Notices

    Topics include design assistance, advisories, and troubleshooting tips. References The most up to date information related to the KCU1250 board and its documentation is available on these websites: KCU1250 Characterization Kit KCU1250 Characterization Kit – Master Answer Record (Xilinx AR63058) These Xilinx documents provide supplemental material useful with this guide: 1.

  • Page 79: Please Read: Important Legal Notices

    Xilinx’s Terms of Sale which can be viewed at http://www.xilinx.com/legal.htm#tos; IP cores may be subject to warranty and support terms contained in a license issued to you by Xilinx. Xilinx products are not designed or intended to be fail-safe or for use in any application requiring fail-safe performance;...
  • Page 80 Mouser Electronics Authorized Distributor Click to View Pricing, Inventory, Delivery & Lifecycle Information: Xilinx CK-U1-KCU1250-G...

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