Xilinx KC705 User Manual page 20

Chapter 1: KC705 Evaluation Board Features
Table 1-5: BPI Flash Memory Connections to the FPGA (Cont'd)
Additional FPGA bitstreams can be stored and used for configuration by setting the Warm
Boot Start Address (WBSTAR) register contained in 7 series FPGAs. More information is
available in the reconfiguration and multiboot section in 7 Series FPGAs Configuration
User Guide (UG470)
the Master BPI configuration mode.
Figure 1-5
For more information about the Micron PC28F00AP30TF part, see
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U1 FPGA Pin Net Name
T22 FLASH_D6
T23 FLASH_D7
U20 FLASH_D8
P29 FLASH_D9
R29 FLASH_D10
P27 FLASH_D11
P28 FLASH_D12
T30 FLASH_D13
P26 FLASH_D14
R26 FLASH_D15
U29 FLASH_WAIT
M25 FPGA_FWE_B
M24 FLASH_OE_B
B10 FPGA_CCLK
U63.6 FLASH_CE_B
M30 FLASH_ADV_B
A10 FPGA_INIT_B
[Ref 2]. The configuration section in this document provides details on
shows the connections of the linear BPI flash memory on the KC705 board.
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U58 BPI Flash Memory
I/O Standard
Pin Number
LVCMOS25 G6
LVCMOS25 H7
LVCMOS25 E1
LVCMOS25 E3
LVCMOS25 F3
LVCMOS25 F4
LVCMOS25 F5
LVCMOS25 H5
LVCMOS25 G7
LVCMOS25 E7
LVCMOS25 F7
LVCMOS25 G8
LVCMOS25 F8
LVCMOS25 E6
LVCMOS25 B4
LVCMOS25 F6
LVCMOS25 D4
UG810 (v1.6.2) August 26, 2015
Pin Name
DQ6
DQ7
DQ8
DQ9
DQ10
DQ11
DQ12
DQ13
DQ14
DQ15
WAIT
WE_B
OE_B
CLK
CE_B
ADV_B
RST_B
[Ref 5].
KC705 Evaluation Board