Xilinx KC705 User Manual page 27

System Clock Source
[Figure
The KC705 board has a 2.5V LVDS differential 200 MHz oscillator (U6) soldered onto the
back side of the board and wired to an FPGA MRCC clock input on bank 33. This 200 MHz
signal pair is named SYSCLK_P and SYSCLK_N, which are connected to FPGA U1 pins
AD12 and AD11 respectively.
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•
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The system clock circuit is shown in
X-Ref Target - Figure 1-10
For more about the Si Time SiT9102 see
Programmable User Clock Source
[Figure
The KC705 board has a programmable low-jitter 3.3V differential oscillator (U45) the
FPGA MRCC inputs of bank 15. This USER_CLOCK_P and USER_CLOCK_N clock signal
pair are connected to FPGA U1 pins K28 and K29 respectively. On power-up the user clock
defaults to an output frequency of 156.250 MHz. User applications can change the output
frequency within the range of 10 MHz to 810 MHz through an I
the KC705 board reverts the user clock to its default frequency of 156.250 MHz.
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KC705 Evaluation Board
UG810 (v1.6.2) August 26, 2015
1-2, callout 7]
Oscillator: Si Time SiT9102AI-243N25E200.00000 (200 MHz)
PPM frequency jitter: 50 ppm
Differential Output
C550
0.1 μF 10V
X5R
GND
Figure 1-10: System Clock Source
1-2, callout 8]
Programmable Oscillator: Silicon Labs Si570BAB0000544DG (10 MHz - 810 MHz)
Differential Output
2
I C address 0x5D
www.xilinx.com
Figure 1-10.
VCC2V5
U6
SIT9102
200 MHz
Oscillator
1 6
OE VCC
2 5
NC OUT_B
3 4
GND OUT
[Ref 6].
Feature Descriptions
SYSCLK_N
R459
100Ω 1%
SYSCLK_P
UG810_c1_10_031214
2
C interface. Power cycling
27
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