Xilinx KC705 User Manual page 12

Chapter 1: KC705 Evaluation Board Features
Each configuration interface corresponds to one or more configuration modes and bus
widths as listed in
4, and 5 respectively as shown in
X-Ref Target - Figure 1-3
The default mode setting is M[2:0] = 010, which selects Master BPI at board power-on.
Refer to the
switch SW13.
Table 1-2: KC705 Board FPGA Configuration Modes
Master SPI
Master BPI
JTAG
For full details on configuring the FPGA, see 7 Series FPGAs Configuration User Guide
(UG470)
Encryption Key Backup Circuit
FPGA U1 implements bitstream encryption key technology. The KC705 board provides the
encryption key backup battery circuit shown in
button-type battery B1 is soldered to the board with the positive output connected to
FPGA U1 VCCBATT pin C10. The battery supply current I
when board power is off. B1 is charged from the VCCAUX_IO 2.0V rail through a series
diode with a typical forward voltage drop of 0.38V. and 4.7 KΩ current limit resistor. The
nominal charging voltage is 1.62V.
12
Send Feedback
Table 1-2. The mode switches M2, M1, and M0 are on SW13 positions 3,
ON Position = 1
Figure 1-3: SW13 Default Settings
Configuration Options, page 73
Configuration Mode
[Ref 2].
www.xilinx.com
Figure 1-3.
1 2 3 4 5
OFF Position = 0
UG810_c1_03_011112
for detailed information about the mode
SW13 DIP Switch
Bus Width
Settings (M[2:0])
x1, x2, x4
001
x8, x16
010
101
Figure 1-4. The rechargeable 1.5V lithium
BATT
CCLK Direction
Output
Output
x1 Not applicable
specification is 150 nA max
KC705 Evaluation Board
UG810 (v1.6.2) August 26, 2015