Xilinx KC705 User Manual page 28

Chapter 1: KC705 Evaluation Board Features
The user clock circuit is shown in
X-Ref Target - Figure 1-11
For more information about the Silicon Labs Si570 see
Reference design files are available to demonstrate how to program the Si570
programmable oscillator. See these files and presentations:
•
•
•
•
User SMA Clock Input
[Figure
An external high-precision clock signal can be provided to the FPGA bank 15 by
connecting differential clock signals through the onboard 50Ω SMA connectors J11 (P) and
J12 (N). The differential clock has signal names are USER_SMA_CLOCK_P and
USER_SMA_CLOCK_N, which are connected to FPGA U1 pins L25 and K25, respectively.
J11 (P) and J12 (N) are connected directly to the noted FPGA pins (no series capacitors and
28
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VCC3V3
R8
4.7KΩ 5%
USER CLOCK SDA
To I 2 C
Bus Switch
USER CLOCK SCL
(U49)
GND
Figure 1-11: User Clock Source
XTP186, KC705 Si570 Programming
RDF0175, KC705 Si570 Programming Design Files
XTP187, KC705 Si570 Fixed Frequencies
RDF0176, KC705 Si570 Fixed Frequencies Design Files
1-2, callout 9]
www.xilinx.com
Figure 1-11.
U45
Si570
Programmable
Oscillator
1 6
NC VDD
2
OE
7
5 USER CLOCK N
SDA
CLK-
8
4 USER CLOCK P
SCL CLK+
3
GND
[Ref 7].
[Ref 8]
[Ref 9]
[Ref 10]
[Ref 11]
VCC3V3
C77
0.01 μF 25V
X7R
GND
10 MHz - 810 MHz
50 PPM
UG810_c1_11_031214
KC705 Evaluation Board
UG810 (v1.6.2) August 26, 2015