Xilinx KC705 User Manual page 22

Chapter 1: KC705 Evaluation Board Features
Four data lines and the FPGA CCLK pin are wired to the Quad SPI flash memory. A
common chip select (FPGA_FCS) shared between the Linear BPI flash memory and the
Quad SPI flash memory is controlled by the configuration mode settings on DIP switch
SW13 position 5 (M0) and a one-of-two demultiplexer device U64. If mode pin M0 = 1, the
SPI flash memory device is selected. If mode pin M0 = 0, the Linear BPI flash memory
device is selected. The connections between the SPI flash memory and the FPGA are listed
in
Table 1-6: Quad SPI Flash Memory Connections to the FPGA
U1 FPGA Pin
Notes:
1. FPGA_FCS connected to FPGA U1 pin U19 becomes QSPI_IC_CS_B through U64 and J3.
The configuration section of7 Series FPGAs Configuration User Guide (UG470)
provides details on using the Quad SPI flash memory.
the Quad SPI flash memory on the KC705 board.
For more information about the Micron N25Q128A13BSF40F part, see
X-Ref Target - Figure 1-6
VCC2V5
R20 R19
DNP 4.7kΩ 5%
FLASH_D3
R429
15Ω 1%
QSPI_IC_CS_B
R430
15Ω 1%
FLASH_D1
22
Send Feedback
Table 1-6.
Net Name
P24 FLASH_D0
R25 FLASH_D1
R20 FLASH_D2
R21 FLASH_D3
B10 FPGA_CCLK
U19 QSPI_IC_CS_B
VCC_SPI
C18
0.1μF 25V
X5R
R21
4.7kΩ 5%
GND
FLASH_D3_R
FLASH_D2_R
Figure 1-6: 128 Mb Quad SPI Flash Memory
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I/O Standard
Pin Number
LVCMOS25
LVCMOS25
LVCMOS25
LVCMOS25
N/A
(1)
LVCMOS25
Figure 1-6
VCC2V5
U7
N25Q128
R17
128 Mb Serial
DNP
Flash Memory
1 16
C
HOLD_B/DQ3
2 15
DQ0
VCC
3 14
NC7
NC0
4 13
NC6
NC1
5 12
NC5
NC2
6 11
NC4
NC3
7 10
VSS
SB
8 9
FLASH_D2_R
WB/VPP/DQ2
DQ1
GND
J1 DDR3 Memory
Pin Name
15 DQ0
8 DQ1
9 DQ2
1 DQ3
16 C
7 S_B
[Ref 2]
shows the connections of
[Ref 5].
R18
4.7kΩ 5%
FPGA_CCLK
FLASH_D0_R FLASH_D0
R432
15Ω 1%
R431
15Ω 1%
FLASH_D2
UG810_c1_06_031214
KC705 Evaluation Board
UG810 (v1.6.2) August 26, 2015