Xilinx KC705 User Manual page 46

Chapter 1: KC705 Evaluation Board Features
The character display runs at 5.0V and is connected to the FPGA's 1.5V HP bank 33
through a Texas Instruments TXS0108E 8-bit bidirectional voltage level translator (U10).
Figure 1-21
X-Ref Target - Figure 1-21
VCC1V5_FPGA
C23
0.1μF 25V
X5R
GND
2
LCD_E_LS 1
LCD_RW_LS 3
LCD_DB4_LS
4
LCD_DB5_LS 5
LCD_DB6_LS
6
LCD_DB7_LS 7
LCD_RS_LS 8
NC 9
10
The KC705 board base board uses a male Samtec MTLW-107-07-G-D-265 2x7 header (J31)
with 0.025-inch square posts on 0.100-inch centers for connecting to a Samtec
SLW-107-01-L-D female socket on the LCD display panel assembly. The LCD header
shown in
X-Ref Target - Figure 1-22
Low Profile Socket
Samtec SLW-107-01-L-D
Low Profile Terminal
Samtec MTLW-107-07-G-D-265
46
Send Feedback
shows the LCD interface circuit.
U10
TXS0108E 8-Bit
Bidirectional
Voltage Level
Translator
19
VCCA VCCB
20
A1 B1
18
A2 B2
17
A3 B3
16
A4 B4
15
A5 B5
14
A6 B6
13
A7 B7
12 NC
A8 B8
11
OE GND
GND
LCD_DB7
LCD_DB5
LCD_E
LCD_RS
GND
Figure 1-21: LCD Interface Circuit
Figure 1-22.
Figure 1-22: LCD Header Details
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VCC5V0
C24
0.1μF 25V
X5R
GND
LCD_E
LCD_RW
LCD_DB4
LCD_DB5
LCD_DB6
LCD_DB7
LCD_RS
VCC5V0
J31
1 2 LCD_DB6
3 4 LCD_DB4
NC 5 6 NC
NC 7 8 NC
9 10 LCD_RW
11 12 LCD_VEE
13 14
LCD Display Assembly
10 mm
KC705 PWA
VCC5V0
R92
6.81kΩ
R133
LCD Contrast
2 kΩ
Potentiometer
GND
UG810_c1_21_031214
UG810_c1_22_031214
KC705 Evaluation Board
UG810 (v1.6.2) August 26, 2015