Xilinx KC705 User Manual page 74

Chapter 1: KC705 Evaluation Board Features
To obtain the fastest configuration speed an external 66 MHz oscillator is wired to the
EMCCLK pin of the FPGA. This allows users to create bitstreams that configure the FPGA
over the 16-bit datapath from the Linear BPI flash memory at a maximum synchronous
read rate of 33 MHz. The bitstream stored in the flash memory must be generated with a
BitGen option to divide the EMCCLK by two.
X-Ref Target - Figure 1-40
SW13
U58
P30 1Gb
Flash Memory
RST_B
CLK
WE_B
OE_B
ADV_B
CE_B
A[27:01]
D[15:00]
U7
N25Q128A13BSF-40F
QUAD SPI
D
Q
HOLD_B
W_B
C
S-B
74
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SW14
GND
Mode
Switch
2.5 V
Part of
SW13
A26
A25
A[26:00]
U63
0
1
Boot Select
Demultiplexer
U64
Oscillator
66 MHz
Figure 1-40: KC705 Board Configuration Circuit
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U1
FPGA
PROG_B
VCCBATT
TCK
TMS
M[2:0]
Bank 0
TDO
INIT_B
CCLK
DONE
FWE_B
FOE_B
ADV_B
Bank 15
RS1
RS0
GND
NC
A[26:25]
A[24:16]
A[15:00]
D[15:00]
Bank 14
FCS_B
CSO_B
PUDC_B
EMCCLK
VCCAUXIO (2.0V)
D11
BAS40-04
TDI
4.7 kΩ
300 Ω
B1
DS20 GND
GREEN
27.4 Ω
GND
ETHERNET MDC
R405
1 kΩ
GND
UG810_c1_40_070114
KC705 Evaluation Board
UG810 (v1.6.2) August 26, 2015