Xilinx KC705 User Manual page 30

Chapter 1: KC705 Evaluation Board Features
The Silicon Labs Si5324 U70 pin 1 reset net SI5326_RST must be driven High to enable the
device. U70 pin 1 net SI5326_RST is level-shifted to VADJ by U75 and is connected to U1
bank 12 pin AE20. An active-Low input performs an external hardware reset of the device.
This resets all internal logic to a known state and forces the device registers to their default
value. The clock outputs are disabled during reset. The part must be programmed after a
reset or power-up to get a clock output. The reset pin 1 has a weak internal pull-up.
The primary purpose of this clock is to support CPRI/OBSAI applications that perform
clock recovery from a user-supplied SFP/SFP+ module and use the jitter attenuated
recovered clock to drive the reference clock inputs of a GTX transceiver. The jitter
attenuated clock circuit is shown in
X-Ref Target - Figure 1-14
X5
114.285 MHz
20 ppm
XA
2
GND1
GND2 XB
4
GND
REC_CLOCK_C_P
R337
100Ω
REC_CLOCK_C_N
SI5326_INT_ALM
SI5326_RST
For more information about the Silicon Labs Si5324 see
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SI5326_VCC
U70
5
10
32
1
SI5326_XTAL_XA 6
3
SI5326_XTAL_XB 7
C475
0.1μF 25V
X5R
REC_CLOCK_P 16
REC_CLOCK_N 17
NC 12
C476
0.1μF 25V
NC 13
X5R
3
NC 4
NC 11
NC 15
NC 18
NC 19
NC 20
1
21
R424
4.7KΩ 5%
GND
Figure 1-14: Jitter Attenuated Clock
www.xilinx.com
Figure 1-14.
Si5324C-C-GM
Clock Multiplier/
Jitter Attenuator
2
NC
VDDA NC1
2
NC
VDDA NC2
2
NC
VDDA NC3
5
NC
XA NC4
8
NC
NC5
29
SI5326_OUT_N
XB CKOUT1_N
28
SI5326_OUT_P
CKOUT1_P
35
NC
CKIN1_P
CKOUT2_N
34
NC
CKOUT2_P
CKIN1_N
CKIN2_P
CKIN2_N
37
GNDPAD
36
INT_C1B CMODE
27
C2B SDI
23
RATE0 SDA_SDO
22
RATE1 SCL
24
LOL A0
31
DEC A1
31
INC A2_SS
9
RST_B
GND1
31
CS_CA
GND2
GND
C473
0.1μF 25V
X5R
SI5326_OUT_C_N
SI5326_OUT_C_P
C474
0.1μF 25V
X5R
NC
SI5326_SDA
SI5326_SCL
UG810_c1_14_031214
[Ref 7].
KC705 Evaluation Board
UG810 (v1.6.2) August 26, 2015