Xilinx Kintex UltraScale KCU1500 User Manual
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Xilinx Kintex UltraScale KCU1500 User Manual

Sdaccel platform acceleration development board
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SDAccel Platform
Reference Design
User Guide
Kintex UltraScale KCU1500
Acceleration Development
Board
UG1234 (v2017.1) June 20, 2017

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Summary of Contents for Xilinx Kintex UltraScale KCU1500

  • Page 1 SDAccel Platform Reference Design User Guide Kintex UltraScale KCU1500 Acceleration Development Board UG1234 (v2017.1) June 20, 2017...

  • Page 2: Revision History

    Reference Design files updated to the 2017.1 SDAccel Environment and updated for the new platform and device. 02/01/2017 2016.4 Updated document and reference design files for compatibility with SDx Environments 2016.4 release. 11/30/2016 2016.3 Initial Xilinx release. Kintex UltraScale KCU1500 Acceleration Development Board Send Feedback UG1234 (v2017.1) June 20, 2017 www.xilinx.com...

  • Page 3: Table Of Contents

    Design Constraints Detail ............41 Kintex UltraScale KCU1500 Acceleration Development Board Send Feedback UG1234 (v2017.1) June 20, 2017...
  • Page 4 Xilinx Resources ........

  • Page 5: Chapter 1: Overview

    Beginning with the 2017.1 SDx Environments release, this reference design and the DSA IMPORTANT: it produces are compatible only with the Kintex UltraScale KCU1500 Acceleration Development Board. They are not compatible with the previous revision of the board (termed Kintex UltraScale Developer Board for Acceleration with KU115), which has different FPGA pinouts and DDR4 memory configurations.

  • Page 6: Platform Features

    Chapter 1: Overview Platform Features The features of the Kintex UltraScale KCU1500 Acceleration development board and the Xilinx Acceleration KCU1500 4DDR Expanded Partial Configuration platform are intended for use as a high-performance acceleration platform for the SDAccel Environment, as follows: •...
  • Page 7 Development Guide (UG1164) [Ref The following chapters describe the platform characteristics, the Hardware Platform, the Software Platform, implementation, as well as the installation, bring-up, and use. Kintex UltraScale KCU1500 Acceleration Development Board Send Feedback UG1234 (v2017.1) June 20, 2017 www.xilinx.com...

  • Page 8: Chapter 2: Platform Characteristics

    Only he logic necessary for keeping the link active and device operational, primarily the Xilinx DMA subsystem for PCI Express, basic control interfaces, and clock sources, is contained within a static “base region” floorplanned to less than 8% of the device area that cannot be used for kernel resources.
  • Page 9 SDAccel System Compiler flow. X-Ref Target - Figure 2-2 Figure 2-2: Device View of Implemented Platform, Showing Base and Expanded Regions Kintex UltraScale KCU1500 Acceleration Development Board Send Feedback UG1234 (v2017.1) June 20, 2017...

  • Page 10: Use With The Sdaccel Environment

    Programmable Region IP core, are configured to use address offsets and ranges that are compatible with the hardware abstraction Layer (HAL) driver provided with the SDx™ Environments installation. The kernel mode drivers for the Xilinx DMA subsystem for PCI Express are likewise provided with the SDx Environments installation.

  • Page 11: Sparse Memory Connectivity

    Programmable Region for user kernels) to the four DDR4 memory controllers using an AXI4 memory-mapped 512-bit data path per instance. It also connects the Xilinx DMA subsystem for PCI Express to all four DDR4 memory controllers using an AXI4 memory-mapped 256-bit data path per instance.

  • Page 12: Stacked Silicon Interconnect (Ssi) Technology Support

    The required physical locations suggest the following design partitioning that is used in the platform: • The Xilinx DMA subsystem for PCIe instance is floorplanned to the static base region of the lower SLR. • The AXI SmartConnect 1x5 (1 slave interface, 5 master interfaces) instance which...
  • Page 13 The combination of static base and reconfigurable expanded region partitioning, with the optimal configuration and careful floorplanning of IP instances, together facilitate the necessary controlled SLR crossing in the KU115 device to effectively utilize both SLRs. Kintex UltraScale KCU1500 Acceleration Development Board Send Feedback UG1234 (v2017.1) June 20, 2017...

  • Page 14: Chapter 3: Hardware Platform

    Chapter 3 Hardware Platform Introduction In this chapter, the hardware architecture of the Xilinx® Acceleration KCU1500 4DDR ® Expanded Partial Configuration platform is described from the perspective of its Vivado integrator block diagram representation, in six parts, as follows: •...
  • Page 15 Figure 3-1: Top-Level IP Integrator Block Diagram - Default View with Interfaces and Wires X-Ref Target - Figure 3-2 Figure 3-2: Top-level IP Integrator Block Diagram - Interface Connections Only View Kintex UltraScale KCU1500 Acceleration Development Board Send Feedback UG1234 (v2017.1) June 20, 2017...

  • Page 16: Host Connectivity

    PCIe block location X0Y0. The platform uses an AXI memory-mapped interface operating at 250 MHz with a 256-bit data width. The basic customization of the Xilinx DMA subsystem for PCIe IP core (herein referred to as the XDMA IP core) is shown in the following figure.
  • Page 17 XDMA IP customization settings. See the DMA Subsystem for PCI Express v3.0 Product Guide (PG195) [Ref 3] for more information on the XDMA IP core, its features, and customizations options. Kintex UltraScale KCU1500 Acceleration Development Board Send Feedback UG1234 (v2017.1) June 20, 2017 www.xilinx.com...

  • Page 18: Memory Control

    The DDR4 IP instances are customized to target the MT40A512M16HA-083E components on the Kintex UltraScale KCU1500 Acceleration development board, with a 512-bit data width, 32-bit address width AXI memory-mapped interface providing high-bandwidth platform fabric access to the full 4GB per channel.
  • Page 19 An outcome of locating the DDR4 memory controllers in the reconfigurable region is that IMPORTANT: DDR4 global memory content is lost when a new partial bitstream is downloaded. Kintex UltraScale KCU1500 Acceleration Development Board Send Feedback UG1234 (v2017.1) June 20, 2017...

  • Page 20: Sdaccel Opencl Programmable Region Ip And The Programmable Region

    Figure 3-8: SDAccel OpenCL Programmable Region IP Core Instance and its Interfaces • The S_AXI interface is an AXI4-Lite slave interface, allowing host control of user kernels. Kintex UltraScale KCU1500 Acceleration Development Board Send Feedback UG1234 (v2017.1) June 20, 2017 www.xilinx.com...
  • Page 21 1x4 AXI Interconnect instance, which also performs domain crossing between CONTROL_CLK and CONTROL_RESET on its slave interface (Programmable Region boundary-facing) side, and DATA_CLK and DATA_RESET on its master interface (kernel-facing) side. Kintex UltraScale KCU1500 Acceleration Development Board Send Feedback UG1234 (v2017.1) June 20, 2017 www.xilinx.com...
  • Page 22 The SDAccel OpenCL Programmable Region IP instance customization Basic tab is shown in the following figure. X-Ref Target - Figure 3-10 Figure 3-10: SDAccel OpenCL Programmable Region IP Customization - Basic Tab Kintex UltraScale KCU1500 Acceleration Development Board Send Feedback UG1234 (v2017.1) June 20, 2017 www.xilinx.com...

  • Page 23: Axi Interconnectivity

    Figure 3-12, the five SmartConnect IP instances together provide both the host and the user kernels with high-performance access to the four DDR4 IP memory controllers. Kintex UltraScale KCU1500 Acceleration Development Board Send Feedback UG1234 (v2017.1) June 20, 2017 www.xilinx.com...
  • Page 24 SDAccel OpenCL Programmable Region IP (and therefore the Programmable Region) for kernel access to global memory, and is synchronous to the kernel clock, driving the aclk2 port. Kintex UltraScale KCU1500 Acceleration Development Board Send Feedback UG1234 (v2017.1) June 20, 2017...
  • Page 25 The second master interface on the static base region 2x3 AXI Interconnect IP allows the management path to access all peripherals on the user path. Kintex UltraScale KCU1500 Acceleration Development Board Send Feedback UG1234 (v2017.1) June 20, 2017...

  • Page 26: Application Profiling And Other Features

    Kintex UltraScale KCU1500 Acceleration development board flash memory programming using SPI flash IP infrastructure • Kintex UltraScale KCU1500 Acceleration development board FPGA fan speed control using memory-mapped I2C controller • AXI Firewall IP protection of the static base region hardware against potential AXI protocol violations from kernels •...

  • Page 27: Clocking And Reset

    AXI-Stream FIFO for interpretation by the SDx Environments application profiling feature. AXI Register Slice instances on the control path ease automatic placement. Clocking and Reset The following sections describe clocking and reset on the Kintex UltraScale KCU1500 Acceleration development board: • Platform Clocking •...
  • Page 28 The XDMA, AXI4-Lite control, kernel clock, kernel clock 2, and AXI Performance Monitor clocks are all derived from the PCIe 100 MHz differential ref_clk top-level input from the Kintex UltraScale KCU1500 Acceleration development board. The following figure shows the base_clocking sub-hierarchy of the static base region.
  • Page 29 GPIO IP core instance named gate_pr is used to hold the reconfigurable expanded region logic, as well as flip-flops at the boundary of the static base region, in reset. Kintex UltraScale KCU1500 Acceleration Development Board Send Feedback UG1234 (v2017.1) June 20, 2017...
  • Page 30 The following figure shows the pr_isolation_expanded static base region level of sub-hierarchy. X-Ref Target - Figure 3-16 Figure 3-16: Partial Reconfiguration Support Logic in pr_isolation_expanded Sub-Hierarchy Kintex UltraScale KCU1500 Acceleration Development Board Send Feedback UG1234 (v2017.1) June 20, 2017 www.xilinx.com...

  • Page 31: Introduction

    Software Platform Introduction The Xilinx® Acceleration KCU1500 4DDR Expanded Partial Configuration platform is a memory-mapped system with PCIe® host connectivity supported by a kernel mode DMA driver for the XDMA IP. A hardware abstraction layer (HAL) driver isolates the SDAccel™...
  • Page 32 S_AXI_ DDR4 channel 0 CTRL controller C0_DDR4_ 0x0007_0000 0x0007_FFFF ddrmem_2 S_AXI_ DDR4 channel 2 CTRL controller C0_DDR4_ 0x0008_0000 0x0008_FFFF ddrmem_3 S_AXI_ DDR4 channel 3 CTRL controller Kintex UltraScale KCU1500 Acceleration Development Board Send Feedback UG1234 (v2017.1) June 20, 2017 www.xilinx.com...
  • Page 33 User Physical Function control path S_AXI_CTL 0x000F_0000 0x000F_FFFF axi_firewall _data AXI Firewall to protect data path S_AXI 0x0010_0000 0x0010_FFFF xilmonitor_ Performance Monitor for application profiling Kintex UltraScale KCU1500 Acceleration Development Board Send Feedback UG1234 (v2017.1) June 20, 2017 www.xilinx.com...
  • Page 34 Debug Bridge for Xilinx Virtual Cable S_AXI 0x0010_0000 0x0010_FFFF xilmonitor_ Performance Monitor for application profiling S_AXI 0x0011_0000 0x0011_0FFF xilmonitor_ fifo0 Trace offload FIFO for application profiling Kintex UltraScale KCU1500 Acceleration Development Board Send Feedback UG1234 (v2017.1) June 20, 2017 www.xilinx.com...
  • Page 35 S_AXI 0000 FFFF DDR4 channel 2 memory-mapped controller data interface M03_AXI C0_DDR4_ 0x3_0000_ 0x3_FFFF_ ddrmem_3 S_AXI 0000 FFFF DDR4 channel 3 memory-mapped controller data interface Kintex UltraScale KCU1500 Acceleration Development Board Send Feedback UG1234 (v2017.1) June 20, 2017 www.xilinx.com...

  • Page 36: Software Layers

    IP cores of the platform by using the provided kernel mode drivers. As provided, the Xilinx Acceleration KCU1500 4DDR Expanded Partial Configuration platform uses an address map compatible with other Xilinx-provided platforms, so the kernel mode drives are not specific to this platform. Kintex UltraScale KCU1500 Acceleration Development Board Send Feedback UG1234 (v2017.1) June 20, 2017...
  • Page 37 C-style APIs to the runtime or other user of the driver. The HAL driver is not specific to the Xilinx Acceleration KCU1500 4DDR Expanded Partial Configuration platform. For more information about the common HAL driver for Hardware...

  • Page 38: Chapter 5: Implementation

    Use the version of Vivado included with your SDx Environments 2017.1 installation. The IMPORTANT: standard Vivado 2017.1 release is not supported when building the Xilinx Acceleration KCU1500 4DDR Expanded Partial Reconfiguration platform. There are two usage flow options for the scripts: 1.
  • Page 39 Implemented (placed run_impl.tcl and routed) design .dsa file for use with write_dsa.tcl SDAccel Figure 5-1: Platform Reference Design Implementation Script Usage Flow Options Kintex UltraScale KCU1500 Acceleration Development Board Send Feedback UG1234 (v2017.1) June 20, 2017 www.xilinx.com...

  • Page 40: Create_Design.tcl Detail

    Sets the version field value in the DSA set_property dsa.version “4.0”\ metadata. [current_project] Sets the flash_offset_address field set_property dsa.flash_offset_address\ value in the DSA metadata. “0x4000000” [current_project] Kintex UltraScale KCU1500 Acceleration Development Board Send Feedback UG1234 (v2017.1) June 20, 2017 www.xilinx.com...

  • Page 41: Design Constraints Detail

    The following code snippet is an example: set_property DONT_TOUCH true [get_cells xcl_design_i/expanded_region] set_property HD.RECONFIGURABLE true [get_cells xcl_design_i/expanded_region] Kintex UltraScale KCU1500 Acceleration Development Board Send Feedback UG1234 (v2017.1) June 20, 2017 www.xilinx.com...
  • Page 42 Some submodules of some of the AXI SmartConnect IP instances are constrained to the upper SLR, as described in Stacked Silicon Interconnect (SSI) Technology Support in Chapter 2. The following code snippet is an example: create_pblock pblock_upper Kintex UltraScale KCU1500 Acceleration Development Board Send Feedback UG1234 (v2017.1) June 20, 2017 www.xilinx.com...
  • Page 43 [get_pblocks pblock_upper] [get_cells [list xcl_design_i/expanded_region/memc/axicc_ddrmem_2_ctrl]] add_cells_to_pblock [get_pblocks pblock_upper] [get_cells [list xcl_design_i/expanded_region/memc/axicc_ddrmem_3_ctrl]] add_cells_to_pblock [get_pblocks pblock_upper] [get_cells [list xcl_design_i/expanded_region/interconnect/interconnect_aximm_ddrmem2/inst/m00_exit_ pipeline]] -quiet resize_pblock [get_pblocks pblock_upper] -add {SLICE_X119Y300:SLICE_X142Y599} resize_pblock [get_pblocks pblock_upper] -add {RAMB18_X15Y120:RAMB18_X17Y239} Kintex UltraScale KCU1500 Acceleration Development Board Send Feedback UG1234 (v2017.1) June 20, 2017 www.xilinx.com...

  • Page 44: Chapter 6: Install, Bring-Up, And Use

    Beginning with the 2017.1 SDx Environments release, this reference design and the IMPORTANT: DSA it produces are compatible only with the new Kintex UltraScale KCU1500 Acceleration Development Board. They are not compatible with the previous revision of the board (termed Kintex UltraScale Developer Board for Acceleration with KU115), which has different FPGA pinouts and DDR4 memory configurations.
  • Page 45 MIG Calibrated: true Firewall Last Error Status: 0x0 (GOOD) 0x0 (GOOD) 0x0 (GOOD) CU Status: 0x4 (IDLE) 0x4 (IDLE) 0x4 (IDLE) 0x4 (IDLE) INFO: xbsak query successful. Kintex UltraScale KCU1500 Acceleration Development Board Send Feedback UG1234 (v2017.1) June 20, 2017 www.xilinx.com...

  • Page 46: Bring-Up Tests

    [Ref Bring-Up Tests With the Kintex UltraScale KCU1500 Acceleration development board installed, DSA programmed, and the xbsak utility indicating compatibility and readiness of the device, it can be useful to compile and execute bring-up tests that use the SDAccel System Compiler flow.
  • Page 47 Chapter 6: Install, Bring-Up, and Use The following information can also be helpful when targeting the xilinx_kcu1500_4ddr-xpr_4_0.dsa from the SDx Environments installation, or as built from the Xilinx Acceleration KCU1500 4DDR Expanded Partial Configuration platform reference design. Device Identification The vendor, build, name, version (VBNV) identifier for the DSA is xilinx:kcu1500:4ddr-xpr:4.0, so an XOCC script (which invokes the SDAccel System...

  • Page 48: Clock Frequency

    See the SDAccel Environment User Guide (UG1023) [Ref 4] and the SDAccel Environment Optimization Guide (UG1027) [Ref 5] for kernel frequency specification, RTL kernels, and related topics. Kintex UltraScale KCU1500 Acceleration Development Board Send Feedback UG1234 (v2017.1) June 20, 2017 www.xilinx.com...
  • Page 49 150 MHz, you should specify such a frequency target: --kernel_frequency 150 In this way, kernel developers can decouple preliminary hardware operation from optimization of kernel code to achieve higher frequencies. Kintex UltraScale KCU1500 Acceleration Development Board Send Feedback UG1234 (v2017.1) June 20, 2017 www.xilinx.com...

  • Page 50: Appendix A: Additional Resources And Legal Notices

    Topics include design assistance, advisories, and troubleshooting tips. Documentation Navigator and Design Hubs Xilinx Documentation Navigator provides access to Xilinx documents, videos, and support resources, which you can filter and search to find information. To open the Xilinx Documentation Navigator (DocNav): ® •...

  • Page 51: References

    Xilinx’s Terms of Sale which can be viewed at https://www.xilinx.com/legal.htm#tos; IP cores may be subject to warranty and support terms contained in a license issued to you by Xilinx. Xilinx products are not designed or intended to be fail-safe or for use in any application requiring fail-safe performance;...

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