Xilinx KC705 User Manual page 34

Chapter 1: KC705 Evaluation Board Features
Table 1-11: PCIe Edge Connector Connections (Cont'd)
Schematic FPGA Pin
Net Name (U1)
PCIE_RX3_N T5
PCIE_RX4_P V6
PCIE_RX4_N V5
PCIE_RX5_P W4
PCIE_RX5_N W3
PCIE_RX6_P Y6
PCIE_RX6_N Y5
PCIE_RX7_P AA4
PCIE_RX7_N AA3
PCIE_TX0_P L4
PCIE_TX0_N L3
PCIE_TX1_P M2
PCIE_TX1_N M1
PCIE_TX2_P N4
PCIE_TX2_N N3
PCIE_TX3_P P2
PCIE_TX3_N P1
PCIE_TX4_P T2
PCIE_TX4_N T1
PCIE_TX5_P U4
PCIE_TX5_N U3
PCIE_TX6_P V2
PCIE_TX6_N V1
PCIE_TX7_P Y2
PCIE_TX7_N Y1
PCIE_CLK_QO_P
U8
PCIE_CLK_QO_N
U7
PCIE_PRSNT_B J32 2, 4, 6
PCIE_WAKE_B
F23
PCIE_PERST_B G25
34
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PCIe Edge PCIe Edge Pin
Connector Pin Name
B28 PETn3
B33 PETp4
B34 PETn4
B37 PETp5
B38 PETn5
B41 PETp6
B42 PETn6
B45 PETp7
B46 PETn7
A16 PERp0
A17 PERn0
A21 PERp1
A22 PERn1
A25 PERp2
A26 PERn2
A29 PERp3
A30 PERn3
A35 PERp4
A36 PERn4
A39 PERp5
A40 PERn5
A43 PERp6
A44 PERn6
A47 PERp7
A48 PERn7
A13 REFCLK+
A14 REFCLK-
A1 PRSNT#1
B11 WAKE#
A11 PERST
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Function
Integrated Endpoint block receive pair
Integrated Endpoint block receive pair
Integrated Endpoint block receive pair
Integrated Endpoint block receive pair
Integrated Endpoint block receive pair
Integrated Endpoint block receive pair
Integrated Endpoint block receive pair
Integrated Endpoint block receive pair
Integrated Endpoint block receive pair
Integrated Endpoint block transmit pair
Integrated Endpoint block transmit pair
Integrated Endpoint block transmit pair
Integrated Endpoint block transmit pair
Integrated Endpoint block transmit pair
Integrated Endpoint block transmit pair
Integrated Endpoint block transmit pair
Integrated Endpoint block transmit pair
Integrated Endpoint block transmit pair
Integrated Endpoint block transmit pair
Integrated Endpoint block transmit pair
Integrated Endpoint block transmit pair
Integrated Endpoint block transmit pair
Integrated Endpoint block transmit pair
Integrated Endpoint block transmit pair
Integrated Endpoint block transmit pair
Integrated Endpoint block differential
clock pair from PCIe
Integrated Endpoint block differential
clock pair from PCIe
J42 Lane Size Select jumper
Integrated Endpoint block wake signal,
not connected on KC705 board
Integrated Endpoint block reset signal
FFG900
Placement
GTXE2_CHANNEL_X0Y4
GTXE2_CHANNEL_X0Y3
GTXE2_CHANNEL_X0Y3
GTXE2_CHANNEL_X0Y2
GTXE2_CHANNEL_X0Y2
GTXE2_CHANNEL_X0Y1
GTXE2_CHANNEL_X0Y1
GTXE2_CHANNEL_X0Y0
GTXE2_CHANNEL_X0Y0
GTXE2_CHANNEL_X0Y7
GTXE2_CHANNEL_X0Y7
GTXE2_CHANNEL_X0Y6
GTXE2_CHANNEL_X0Y6
GTXE2_CHANNEL_X0Y5
GTXE2_CHANNEL_X0Y5
GTXE2_CHANNEL_X0Y4
GTXE2_CHANNEL_X0Y4
GTXE2_CHANNEL_X0Y3
GTXE2_CHANNEL_X0Y3
GTXE2_CHANNEL_X0Y2
GTXE2_CHANNEL_X0Y2
GTXE2_CHANNEL_X0Y1
GTXE2_CHANNEL_X0Y1
GTXE2_CHANNEL_X0Y0
GTXE2_CHANNEL_X0Y0
MGT_BANK_115
MGT_BANK_115
N/A
N/A
N/A
KC705 Evaluation Board
UG810 (v1.6.2) August 26, 2015