Xilinx KC705 User Manual page 62

Chapter 1: KC705 Evaluation Board Features
LPC Connector J2
[Figure
The 160-pin LPC connector defined by the FMC specification
provides connectivity for up to:
•
•
•
•
•
The connections between the LPC connector at J2 and FPGA U1
subset of this connectivity:
•
•
•
•
•
Table 1-29: LPC Connections, J2 to FPGA U1
J2
Schematic Net Name
Pin
C2 FMC_LPC_DP0_C2M_P
C3 FMC_LPC_DP0_C2M_N
C6 FMC_LPC_DP0_M2C_P
C7 FMC_LPC_DP0_M2C_N
C10 FMC_LPC_LA06_P
C11 FMC_LPC_LA06_N
C14 FMC_LPC_LA10_P
C15 FMC_LPC_LA10_N
C18 FMC_LPC_LA14_P
C19 FMC_LPC_LA14_N
C22 FMC_LPC_LA18_CC_P
C23 FMC_LPC_LA18_CC_N
C26 FMC_LPC_LA27_P
C27 FMC_LPC_LA27_N
C30 FMC_LPC_IIC_SCL
C31 FMC_LPC_IIC_SDA
62
Send Feedback
1-2, callout 31]
68 single-ended or 34 differential user-defined signals
1 GTX transceiver
1 GTX clock
2 differential clocks
61 ground and 10 power connections
34 differential user defined pairs
• 34 LA pairs (LA00-LA33)
1 GTX transceiver
1 GTX clock
2 differential clocks
61 ground and 9 power connections
U1
I/O Standard FPGA
Pin
F2
F1
F6
F5
LVDS AK20
LVDS AK21
LVDS AJ24
LVDS AK25
LVDS AD21
LVDS AE21
LVDS AD27
LVDS AD28
LVDS AJ28
LVDS AJ29
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J2
Schematic Net Name
Pin
D1 PWRCTL1_VCC4A_PG
D4 FMC_LPC_GBTCLK0_M2C_P
D5 FMC_LPC_GBTCLK0_M2C_N
D8 FMC_LPC_LA01_CC_P
D9 FMC_LPC_LA01_CC_N
D11 FMC_LPC_LA05_P
D12 FMC_LPC_LA05_N
D14 FMC_LPC_LA09_P
D15 FMC_LPC_LA09_N
D17 FMC_LPC_LA13_P
D18 FMC_LPC_LA13_N
D20 FMC_LPC_LA17_CC_P
D21 FMC_LPC_LA17_CC_N
D23 FMC_LPC_LA23_P
D24 FMC_LPC_LA23_N
D26 FMC_LPC_LA26_P
(Figure B-2, page 80)
(Table 1-29) implement a
U1
I/O Standard FPGA
Pin
LVDS N8
LVDS N7
LVDS AE23
LVDS AF23
LVDS AG22
LVDS AH22
LVDS AK23
LVDS AK24
LVDS AB24
LVDS AC25
LVDS AB27
LVDS AC27
LVDS AH26
LVDS AH27
LVDS AK29
KC705 Evaluation Board
UG810 (v1.6.2) August 26, 2015