Xilinx KC705 User Manual page 40

Chapter 1: KC705 Evaluation Board Features
SGMII GTX Transceiver Clock Generator
[Figure
An Integrated Circuit Systems ICS844021I chip (U2) generates a high-quality, low-jitter,
125 MHz LVDS clock from a 25 MHz crystal (X3). This clock is sent to FPGA U1, bank 117
GTX transceiver (clock pins G8 (P) and G7 (N)) driving the SGMII interface. Series AC
coupling capacitors are present to allow the clock input of the FPGA to set the common
mode voltage.
X-Ref Target - Figure 1-18
C93
18pF 50V
NPO
X3
25.00 MHz
2
R134
GND2
1.0MΩ 5%
C94
GND2
4
18pF 50V
NPO
GND_SGMIICLK GND_SGMIICLK
Table 1-18
Table 1-18: Ethernet PHY Connections
40
Send Feedback
1-2, callout 16]
Figure 1-18 shows the Ethernet SGMII clock source.
VDDA_SGMIICLK
1
X1 SGMIICLK_XTAL_OUT
3
X2 SGMIICLK_XTAL_IN
Figure 1-18: Ethernet 125 MHz SGMII GTX Clock
shows the connections and pin numbers for the M88E1111 PHY.
U1 FPGA Pin Schematic Net Name
J21 PHY_MDIO
R23 PHY_MDC
N30 PHY_INT
L20 PHY_RESET
R30 PHY_CRS
W19 PHY_COL
U27 PHY_RXCLK
V26 PHY_RXER
R28 PHY_REXCTL_RXDV
U30 PHY_RXD0
U25 PHY_RXD1
T25 PHY_RXD2
U28 PHY_RXD3
R19 PHY_RXD4
T27 PHY_RXD5
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VDD_SGMIICLK
U2
ICS844021I-01
Clock Generator
5
OE
8
1
VDDA VDD
7
3 SGMIICLK_Q0_C_P
XTAL_OUT Q0
6
4 SGMIICLK_Q0_C_N
XTAL_IN NQ0
2
GND
GND_SGMIICLK
I/O Standard
LVCMOS25
LVCMOS25
LVCMOS25
LVCMOS25
LVCMOS25
LVCMOS25
LVCMOS25
LVCMOS25
LVCMOS25
LVCMOS25
LVCMOS25
LVCMOS25
LVCMOS25
LVCMOS25
LVCMOS25
C14
0.1μF 25V
X5R
SGMIICLK_Q0_P
SGMIICLK_Q0_N
C15
0.1μF 25V
X5R
UG810_c1_18_031214
M88E1111 (U37)
Pin Number Pin Name
M1 MDIO
L3 MDC
L1 INT_B
K3 RESET_B
B5 CRS
B6 COL
C1 RXCLK
D2 RXER
B1 RXDV
B2 RXD0
D3 RXD1
C3 RXD2
B3 RXD3
C4 RXD4
A1 RXD5
KC705 Evaluation Board
UG810 (v1.6.2) August 26, 2015