Pci Express Edge Connector - Xilinx KC705 User Manual

PCI Express Edge Connector

[Figure
The 8-lane PCI Express edge connector performs data transfers at the rate of 2.5 GT/s for a
Gen1 application and 5.0 GT/s for a Gen2 application. The PCIe transmit and receive
signal datapaths have a characteristic impedance of 85Ω ±10%. The PCIe clock is routed as
a 100Ω differential pair. The 7 series FPGAs GTX transceivers are used for multi-gigabit per
second serial interfaces.
The XC7K325T-2FFG900C FPGA (-2 speed grade) included with the KC705 board supports
up to Gen2 x8.
The PCIe clock is input from the edge connector. It is AC coupled to the FPGA through the
MGTREFCLK1 pins of Quad 115. PCIE_CLK_Q0_P is connected to FPGA U1 pin U8, and
the _N net is connected to pin U7. The PCI Express clock circuit is shown in
X-Ref Target - Figure 1-15
PCIe lane width/size is selected via jumper J32
selection is 8-lane (J32 pins 5 and 6 jumpered).
X-Ref Target - Figure 1-16
Table 1-11
Table 1-11: PCIe Edge Connector Connections
Schematic FPGA Pin
Net Name (U1)
PCIE_RX0_P M6
PCIE_RX0_N M5
PCIE_RX1_P P6
PCIE_RX1_N P5
PCIE_RX2_P R4
PCIE_RX2_N R3
PCIE_RX3_P T6
KC705 Evaluation Board
UG810 (v1.6.2) August 26, 2015
1-2, callout 13]
P1
PCI Express
Eight-Lane
Edge connector
OE
GND
REFCLK+
REFCLK-
GND
Figure 1-15: PCI Express Clock
PCIE_PRSNT_X1
PCIE_PRSNT_X4
PCIE_PRSNT_X8
Figure 1-16: PCI Express Lane Size Select Jumper J32
lists the PCIe edge connector connections.
PCIe Edge PCIe Edge Pin
Connector Pin Name
B14 PETp0
B15 PETn0
B19 PETp1
B20 PETn1
B23 PETp2
B24 PETn2
B27 PETp3
www.xilinx.com
C544
0.01μF 25V
A12
X7R
A13
PCIE_CLK_Q0_C_P
A14
PCIE_CLK_Q0_C_N
A15
C545
0.01μF 25V
X7R
GND
(Figure
J32
PCIE_PRSNT_B
1 2
3 4
5 6
UG810_c1_16_031214
Function
Integrated Endpoint block receive pair
Integrated Endpoint block receive pair
Integrated Endpoint block receive pair
Integrated Endpoint block receive pair
Integrated Endpoint block receive pair
Integrated Endpoint block receive pair
Integrated Endpoint block receive pair
Feature Descriptions
Figure
PCIE_CLK_Q0_P
PCIE_CLK_Q0_N
UG810_c1_15_031214
1-16). The default lane size
FFG900
Placement
GTXE2_CHANNEL_X0Y7
GTXE2_CHANNEL_X0Y7
GTXE2_CHANNEL_X0Y6
GTXE2_CHANNEL_X0Y6
GTXE2_CHANNEL_X0Y5
GTXE2_CHANNEL_X0Y5
GTXE2_CHANNEL_X0Y4
Send Feedback
1-15.
33