Xilinx KC705 User Manual page 72

Chapter 1: KC705 Evaluation Board Features
X-Ref Target - Figure 1-38
XADC_VCC5V0
VADJ
Table 1-34
Table 1-34: XADC Header J46 Pinout
Net Name J46 Pin Number
VN, VP
XADC_VAUX0P, N
XADC_VAUX8N, P
DXP, DXN
XADC_AGND
XADC_VREF
XADC_VCC5V0
XADC_VCC_HEADER
VADJ
GND
XADC_GPIO_3, 2, 1, 0
72
Send Feedback
XADC_VN
XADC_VAUX0P
XADC_VAUX8N
XADC_DXP
XADC_VREF
XADC_GPIO_1
XADC_GPIO_3
Figure 1-38: XADC Header (J46)
describes the XADC header J46 pin functions.
1, 2 Dedicated analog input channel for the XADC.
Auxiliary analog input channel 0. Also supports use as I/O inputs when
3, 6
anti alias capacitor is not present.
Auxiliary analog input channel 8. Also supports use as I/O inputs when
7, 8
anti alias capacitor is not present.
9, 12 Access to thermal diode.
4, 5, 10 Analog ground reference.
11 1.25V reference from the board.
13 Filtered 5V supply from board.
14 Analog 1.8V supply for XADC.
15 VCCO supply for bank which is the source of DIO pins.
16 Digital Ground (board) Reference
Digital I/O. These pins should come from the same bank. These I/Os
19, 20, 17, 18 should not be shared with other functions because they are required to
support 3-state operation.
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J46
1 2
3 4
5 6 XADC_VAUX0N
7 8 XADC_VAUX8P
9 10
11 12
XADC_VCC_HEADER
13 14
15 16
XADC_GPIO_0
17 18
XADC_GPIO_2
19 20
GND
XADC_AGND XADC_AGND
Description
UG810 (v1.6.2) August 26, 2015
XADC_VP
XADC_DXN
UG810_c1_38_031214
KC705 Evaluation Board