Usb-To-Uart Bridge - Xilinx KC705 User Manual

Table 1-18: Ethernet PHY Connections (Cont'd)
Details about the tri-mode Ethernet MAC core are provided in LogiCORE IP Tri-Mode
Ethernet MAC User Guide (PG051)
For more information about the Marvell 88E1111, see
For more information about the ICS 844021-01, see

USB-to-UART Bridge

[Figure
The KC705 board contains a Silicon Labs CP2103GM USB-to-UART bridge device (U12)
which allows a connection to a host computer with a USB port. The USB cable is supplied
in the Evaluation Kit (standard-A plug to host computer, mini-B plug to KC705 board
connector J6). The CP2103GM is powered by the USB 5V provided by the host PC when the
USB cable is plugged into the USB port on the KC705 board.
Xilinx UART IP is expected to be implemented in the FPGA fabric. The FPGA supports the
USB-to-UART bridge using four signal pins: Transmit (TX), Receive (RX), Request to Send
(RTS), and Clear to Send (CTS).
KC705 Evaluation Board
UG810 (v1.6.2) August 26, 2015
U1 FPGA Pin Schematic Net Name
T26 PHY_RXD6
T28 PHY_RXD7
K30 PHY_TXC_GTXCLK
M28 PHY_TXCLK
N29 PHY_TXER
M27 PHY_TXCTL_TXEN
N27 PHY_TXD0
N25 PHY_TXD1
M29 PHY_TXD2
L28 PHY_TXD3
J26 PHY_TXD4
K26 PHY_TXD5
L30 PHY_TXD6
J28 PHY_TXD7
J4 SGMII_TX_P
J3 SGMII_TX_N
H6 SGMII_RX_P
H5 SGMII_RX_N
1-2, callout 17]
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I/O Standard
LVCMOS25
LVCMOS25
LVCMOS25
LVCMOS25
LVCMOS25
LVCMOS25
LVCMOS25
LVCMOS25
LVCMOS25
LVCMOS25
LVCMOS25
LVCMOS25
LVCMOS25
LVCMOS25
LVCMOS25
LVCMOS25
LVCMOS25
LVCMOS25
[Ref 14].
[Ref 15].
[Ref 16].
Feature Descriptions
M88E1111 (U37)
Pin Number Pin Name
A2 RXD6
C5 RXD7
E2 GTXCLK
D1 TXCLK
F2 TXER
E1 TXEN
F1 TXD0
G2 TXD1
G3 TXD2
H2 TXD3
H1 TXD4
H3 TXD5
J1 TXD6
J2 TXD7
A3 SIN_P
A4 SIN_N
A7 SOUT_P
A8 SOUT_N
41
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