Xilinx KC705 User Manual page 38

Chapter 1: KC705 Evaluation Board Features
Table 1-14
Table 1-14: FPGA U1 to SFP+ Module Connections
Notes:
1. On KC705 boards prior to Rev 1.1, SFP+ connector P5 pin 18 RD_P is connected to net SFP_RX_N, and
2. On KC705 boards prior to Rev 1.1, SFP+ connector P5 pin 18 TD_P is connected to net SFP_TX_N, and
3. SFP_TX_DISABLE_TRANS I/O standard = LVCMOS25.
Table 1-15
Table 1-15: SFP+ Module Control and Status
SFP_TX_FAULT
SFP_TX_DISABLE
SFP_MOD_DETECT
SFP_RS0
SFP_RS1
38
Send Feedback
lists the SFP+ module RX and TX connections to the FPGA.
FPGA Pin
(U1)
G3
G4
H1
H2
Y20 SFP_TX_DISABLE_TRANS
pin 19 RD_N is connected to net SFP_RX_P.
pin 19 TD_N is connected to net SFP_TX_P.
lists the SFP+ module control and status connections to the FPGA.
SFP Control/Status Signal
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Schematic
Net Name
SFP_RX_N
SFP_RX_P
SFP_TX_N
SFP_TX_P
(3)
Board Connection
Test Point J10
High = Fault
Low = Normal Operation
Jumper J4
Off = FP Disabled
On = SFP Enabled
Test Point J9
High = Module Not Present
Low = Module Present
Jumper J27
Jumper Pins 1-2 = Full RX Bandwidth
Jumper Pins 2-3 = Reduced RX Bandwidth
Jumper J28
Jumper Pins 1-2 = Full TX Bandwidth
Jumper Pins 2-3 = Reduced TX Bandwidth
SFP+ Pin SFP+ Pin Name
(P5) (P5)
12 RD_N
13 RD_P
19 TX_N
(2)
18 TX_P
3 TX_DISABLE
KC705 Evaluation Board
UG810 (v1.6.2) August 26, 2015
(1)
(1)
(2)