Revision History - Xilinx KC705 User Manual

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Revision History

The following table shows the revision history for this document.
Date Version
08/26/2015 1.6.2
04/13/2015 1.6.1
12/08/2014 1.6
KC705 Evaluation Board
In Table 1-9, the I/O standard for SYSCLK_N and SYSCLK_P were updated to LVDS. In
Table 1-27, under Directional Pushbutton Switches, the I/O standard for GPIO_SW_C
was updated to LVCMOS25. Updated the #USB UART section of
Constraints File Listing.
In HPC Connector J22, page
Added a note about jumper header locations below
heading J1 DDR3 Memory to U58 BPI Flash Memory. Parts PC28F00AP30TF and
N25Q128A13BSF40F changed from Numonyx to Micron. Described J11 and J12
connections in User SMA Clock Input, page
User Clock Source, page 27: XTP186 became XTP204, RDF0175 became RDF0194,
XTP187 became XTP203, and RDF0176 became RDF0193. Corrected the device in the
heading of Table 1-20 from CP2013 to CP2103. Updated
2
Updated Table 1-24 I C devices. In
Replaced Table A-3, KC705 Default Jumper Settings and added
jumper locations. Replaced the constraints file in
Listing. Added information about ordering the custom ATX cable to
Additional Resources, [Ref
www.xilinx.com
Revision
57, the GTX clock count changed from 1 to 2. Updated links.
Table
28. Made these updates in
Table 1-28, J22 pin G7 connects to FPGA U1 pin C27.
Appendix C, Master Constraints File
20].
Appendix C, Master
1-1. Changed Table 1-5
Programmable
I2C Bus Switch, page 47.
Figure A-3
to show
Appendix F,
UG810 (v1.6.2) August 26, 2015