Overview - Xilinx Virtex-7 FPGA VC7222 IBERT Getting Started Manual

VC7222 IBERT Getting Started Guide

Overview

This document provides a procedure for setting up the Virtex®-7 FPGA VC7222 GTH and
GTZ Transceiver Characterization Board to run the Integrated Bit Error Ratio Test (IBERT)
demonstration using the Vivado® Design Suite. The designs required to run the IBERT
demonstration are stored in the Secure Digital (SD) memory card provided with the
VC7222 board. A copy of the designs can also be found at the
Characterization Kit documentation
The VC7222 board is described in detail in Virtex-7 FPGA VC7222 GTH and GTZ Transceiver
Characterization Board User Guide (UG965)
The IBERT GTH demonstration operates one GTH Quad at a time. The procedure
consists of:
The IBERT GTZ demonstration operates 8 GTZ lanes using both Q300A and Q300B. The
procedure consists of:
VC7222 IBERT Getting Started Guide
UG971 (v5.0) June 12, 2014
• Setting Up the VC7222 Board for GTH and GTZ IBERT Testing, page 6
• Extracting the Project Files, page 7
• Connecting the GTH Transceivers and Reference Clocks, page 8
• Configuring the FPGA, page 13
• Setting Up the Vivado Design Suite Software, page 15
• Starting the SuperClock-2 Module, page 18
• Viewing GTH Transceiver Operation, page 24
• Closing the IBERT Demonstration, page 25
• Connecting the GTZ Transceiver and Reference Clocks, page 25
• Configuring the FPGA, page 30
• Setting up the Vivado Design Suite Software, page 31
• Starting the SuperClock-2 Module, page 18
• Viewing the GTZ Transceiver Operation, page 38
• Closing the IBERT Demonstration, page 39
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Virtex-7 FPGA VC7222
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