Revision History - Xilinx Virtex-7 FPGA VC7222 IBERT Getting Started Manual

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Revision History

The following table shows the revision history for this document.
Date Version
09/20/2013 1.0
09/24/2013 1.0.1
11/07/2013 2.0
01/22/2014 3.0
04/16/2014 4.0
06/12/2014 5.0
VC7222 IBERT Getting Started Guide
Initial Xilinx release.
Updated the DISCLAIMER, page
Updated for Vivado® Design Suite 2013.3. Updated most figures in
IBERT Getting Started Guide.
File Hierarchy. Deleted Figures 2-12 and Figure 3-9, Synthesize Out-Of-Context Module. The
name of the project ZIP file changed to rdf0297-vc7222-ibert-2013-3.zip.
Replaced Figure 3-8, Set As Out Of Context Module with Design Sources File Hierarchy
screen. Deleted Figure 3-12, Edit the Implementation Setting. Updated
Additional Resources links.
Updated for Vivado Design Suite 2013.4. Updated
Figure 1-15, Figure 1-27, Figure
Updated for Vivado Design Suite 2014.1. Updated 30 graphics in Chapters 1, 2, and 3.
File lists changed under Extracting the Project
to rdf0297-vc7222-ibert-2014-1.zip. Launching the Vivado Design Suite Software
was changed to Setting Up the Vivado Design Suite Software in the
Demonstration and Running the GTZ IBERT Demonstration
Bit Errors was added to both sections.
Updated for Vivado Design Suite 2014.2. Updated
Figure 1-20, Figure 1-23, Figure
Figure 2-8, Figure 2-11, Figure
Figure 3-8, Figure 3-11. and
and Viewing the GTZ Transceiver
www.xilinx.com
Revision
2.
Figure 1-31 and Figure 2-11
Figure
1-28, Figure 1-29, Figure
Files. The ZIP project file name changed
Figure
1-27, Figure 1-30, Figure
2-14, Figure 2-16, Figure
Figure 3-13. Updated Viewing GTH Transceiver Operation
Operation.
Chapter 1, VC7222
were renamed Design Sources
Appendix A,
1-11, Figure 1-13, Figure
1-33, Figure 2-1, and Figure
Running the GTH IBERT
sections, and In Case of RX
1-10, Figure 1-11, Figure
1-33, Figure 2-1, Figure 2-4,
3-2, through Figure 3-5,
UG971 (v5.0) June 12, 2014
1-14,
3-5.
1-19,