Xilinx Virtex-7 FPGA VC7222 IBERT Getting Started Manual page 47

9.
X-Ref Target - Figure 2-7
VC7222 IBERT Getting Started Guide
UG971 (v5.0) June 12, 2014
In the Clock Settings tab, select DIFF SSTL15 for the I/O Standard, enter AL24 for P
Package Pin and AL25 for N Package Pin (the FPGA pins that the system clock
connects to), and ensure the Frequency is set to 200.00
Generate in the next window to generate the output products.
Figure 2-7: Customize IP - Clock Settings
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(Figure 2-7). Click OK. Click
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