Chapter 3: Creating The Gtz Ibert Core - Xilinx Virtex-7 FPGA VC7222 IBERT Getting Started Manual

Creating the GTZ IBERT Core
This section provides a procedure to create the GTZ IBERT core with integrated
SuperClock-2 controller. Vivado® Design Suite 2014.2 is required to rebuild the design
shown here.
For more details on generating IBERT cores, see the Vivado Design Suite User Guide:
Programming and Debugging (UG908)
Note:
core.
1.
X-Ref Target - Figure 3-1
VC7222 IBERT Getting Started Guide
UG971 (v5.0) June 12, 2014
See steps 1–5 in Chapter 2, Creating the GTH IBERT Core
In the IP Catalog window expand the Debug & Verification folder, then expand
the Debug folder. Double-click or right-click the IBERT 7 Series GTZ to run the
GTZ configuration wizard
www.xilinx.com
[Ref 3].
(Figure 3-1).
Figure 3-1: IP Catalog
Chapter 3
to learn how to create a new IP
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