Attach The Gth Quad Connector - Xilinx Virtex-7 FPGA VC7222 IBERT Getting Started Manual

Chapter 1: VC7222 IBERT Getting Started Guide
The four SMA pairs labeled CLKOUT provide LVDS clock outputs from the Si5368 clock
multiplier/jitter attenuator device on the clock module. The SMA pair labeled Si570_CLK
provides LVDS clock output from the Si570 programmable oscillator on the clock module.
Note:
SuperClock-2 module.
For the GTH IBERT demonstration, the output clock frequencies are preset to 325.00 MHz.
For more information regarding the SuperClock-2 module, see the HW-CLK-101-SCLK2
SuperClock-2 Module User Guide (UG770)

Attach the GTH Quad Connector

Before connecting the BullsEye cable assembly to the board, firmly secure the blue
elastomer seal provided with the cable assembly to the bottom of the connector housing, if
it is not already inserted (see
Note:
X-Ref Target - Figure 1-4
10
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The Si570 oscillator does not support LVDS output on Rev. B and earlier revisions of the
Figure
Figure 1-4 is for reference only and might not reflect the current version of the connector.
Figure 1-4: BullsEye Connector with Elastomer Seal
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[Ref 2].
1-4).
VC7222 IBERT Getting Started Guide
UG971 (v5.0) June 12, 2014