Overview - Xilinx Virtex-7 FPGA VC7222 Getting Started Manual

VC7222 IBERT Getting Started Guide

Overview

This document provides a procedure for setting up the Virtex®-7 FPGA VC7222 GTH and
GTZ Transceiver Characterization Board to run the Integrated Bit Error Ratio Test (IBERT)
demonstration using the Vivado® Design Suite. The designs required to run the IBERT
demonstration are stored in the Secure Digital (SD) memory card provided with the VC7222
board. A copy of the designs can also be found at the
Characterization Kit documentation
The VC7222 board is described in detail in Virtex-7 FPGA VC7222 GTH and GTZ Transceiver
Characterization Board User Guide (UG965)
The IBERT GTH demonstration operates one GTH Quad at a time. The procedure consists of:
1. Setting Up the VC7222 Board for GTH and GTZ IBERT Testing, page 7
2. Extracting the Project Files, page 7
3. Connecting the GTH Transceivers and Reference Clocks, page 9
4. Configuring the FPGA, page 15
5. Setting Up the Vivado Design Suite, page 17
6. Starting the SuperClock-2 Module, page 20
7. Viewing GTH Transceiver Operation, page 26
8. Closing the IBERT Demonstration, page 27
The IBERT GTZ demonstration operates 8 GTZ lanes using both Q300A and Q300B. The
procedure consists of:
1. Connecting the GTZ Transceiver and Reference Clocks, page 28
2. Configuring the FPGA, page 33
3. Setting up the Vivado Design Suite, page 35
4. Starting the SuperClock-2 Module, page 20
VC7222 IBERT Getting Started Guide
UG971 (Vivado Design Suite v2015.1) April 27, 2015
Virtex-7 FPGA VC7222
website.
[Ref 1].
www.xilinx.com
Chapter 1
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