Xilinx Virtex-7 FPGA VC7222 IBERT Getting Started Manual page 9

All GTH transceiver pins and reference clock pins are routed from the FPGA to a connector
pad which interfaces with the Samtec BullsEye connectors.
connector pad, and
X-Ref Target - Figure 1-2
The SuperClock-2 module provides LVDS clock outputs for the GTH transceiver reference
clock in the IBERT demonstration.
SMA connections on the clock module which can be connected to the reference clock
cables.
Note:
board.
X-Ref Target - Figure 1-3
VC7222 IBERT Getting Started Guide
UG971 (v5.0) June 12, 2014
Figure 1-2 B shows the connector pinout.
Figure 1-2: A – GTH Connector Pad. B – GTH Connector Pinout
The image in Figure 1-3 is for reference only and might not reflect the current revision of the
Figure 1-3: SuperClock-2 Module Output Clock SMA Locations
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Running the GTH IBERT Demonstration
Figure 1-2
Figure 1-3 shows the location of the differential clock
A shows the
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