Extracting The Project Files - Xilinx Virtex-7 FPGA VC7222 IBERT Getting Started Manual

Extracting the Project Files

The Vivado project files required to run the IBERT demonstration are located in
rdf0297-vc7222-ibert-2014-2.zip on the SD card provided with the VC7222
board. These files are also available online at the
Kit documentation
The ZIP file contains these files:
•
•
•
The Tcl scripts are used to help merge the IBERT and SuperClock-2 source code (described
in
Core) and to set up the SuperClock-2 module (described in
Module, page 18
GTZ section).
To copy the files from the SD memory card:
1.
2.
3.
VC7222 IBERT Getting Started Guide
UG971 (v5.0) June 12, 2014
d. Screw down a 50Ω SMA terminator onto each of the six unused Si5368 clock
output SMA connectors: J7, J8, J12, J15, J16, and J17.
website.
BIT files
vc7222_ibert_q113_325.bit
vc7222_ibert_q114_325.bit
vc7222_ibert_q115_325.bit
vc7222_ibert_q213_325.bit
vc7222_ibert_q214_325.bit
vc7222_ibert_q215_325.bit
vc7222_ibert_q300_225.bit
vc7222_uarttest.bit
Probe files
vc7222_ibert_q113_debug_nets.ltx
vc7222_ibert_q114_debug_nets.ltx
vc7222_ibert_q115_debug_nets.ltx
vc7222_ibert_q213_debug_nets.ltx
vc7222_ibert_q214_debug_nets.ltx
vc7222_ibert_q215_debug_nets.ltx
vc7222_ibert_q300_debug_nets.ltx
Tcl scripts
add_scm2.tcl
setup_scm2_325_00_GTH.tcl
setup_scm2_225_00_GTZ.tcl
Chapter 2, Creating the GTH IBERT Core
in the GTH section and
Connect the SD card to the host computer.
Locate the file rdf0297-vc7222-ibert-2014-2.zip on the SD memory card.
Unzip the files to a working directory on the host computer.
www.xilinx.com
Extracting the Project Files
Virtex-7 FPGA VC7222 Characterization
and in Chapter 3, Creating the GTZ IBERT
Starting the SuperClock-2
Starting the SuperClock-2 Module, page 31
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in the
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