Chapter 1: Vc7203 Ibert Getting Started Guide; Overview - Xilinx Virtex-7 FPGA VC7203 Getting Started Manual

VC7203 IBERT Getting Started Guide

Overview

This document provides a procedure for setting up the VC7203 Virtex®-7 FPGA GTX
Transceiver Characterization Board to run the Integrated Bit Error Ratio Test (IBERT)
demonstration using the Vivado® Design Suite. The designs that are required to run the
IBERT demonstration are stored in a Secure Digital (SD) memory card that is provided
with the VC7203 board. The demonstration shows the capabilities of the Virtex-7
XC7V485T FPGA GTX transceiver.
The VC7203 board is described in detail in VC7203 Virtex-7 FPGA GTX Transceiver
Characterization Board User Guide (UG957).
The IBERT demonstrations operate one GTX Quad at a time. The procedure consists of:
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VC7203 IBERT Getting Started Guide
UG847 (v3.0) July 10, 2013
Setting Up the VC7203 Board
Extracting the Project Files
Connecting the GTX Transceivers and Reference Clocks
Configuring the FPGA
Launching the Vivado Design Suite Software
Starting the SuperClock-2 Module
Viewing GTX Transceiver Operation
Closing the IBERT Demonstration
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Overview
Chapter 1
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